void setESI(uint32_t value) { _registers.__esi = value; }
uint32_t getEDI() const { return _registers.__edi; }
void setEDI(uint32_t value) { _registers.__edi = value; }
+ uint32_t getWCookie() const { return 0; }
private:
struct GPRs {
void setR14(uint64_t value) { _registers.__r14 = value; }
uint64_t getR15() const { return _registers.__r15; }
void setR15(uint64_t value) { _registers.__r15 = value; }
+ uint64_t getWCookie() const { return 0; }
private:
struct GPRs {
void setSP(uint32_t value) { _registers.__r1 = value; }
uint64_t getIP() const { return _registers.__srr0; }
void setIP(uint32_t value) { _registers.__srr0 = value; }
+ uint64_t getWCookie() const { return 0; }
private:
struct ppc_thread_state_t {
void setIP(uint64_t value) { _registers.__pc = value; }
uint64_t getFP() const { return _registers.__fp; }
void setFP(uint64_t value) { _registers.__fp = value; }
+ uint64_t getWCookie() const { return 0; }
private:
struct GPRs {
void setSP(uint32_t value) { _registers.__sp = value; }
uint32_t getIP() const { return _registers.__pc; }
void setIP(uint32_t value) { _registers.__pc = value; }
+ uint64_t getWCookie() const { return 0; }
void saveVFPAsX() {
assert(_use_X_for_vfp_save || !_saved_vfp_d0_d15);
void setSP(uint32_t value) { _registers.__r[1] = value; }
uint64_t getIP() const { return _registers.__r[9]; }
void setIP(uint32_t value) { _registers.__r[9] = value; }
+ uint64_t getWCookie() const { return 0; }
private:
struct or1k_thread_state_t {
}
#endif // _LIBUNWIND_TARGET_OR1K
+
+
+#if defined(_LIBUNWIND_TARGET_SPARC64)
+/// Registers_sparc64 holds the register state of a thread in a 64-bit
+/// sparc process.
+class _LIBUNWIND_HIDDEN Registers_sparc64 {
+public:
+ Registers_sparc64();
+ Registers_sparc64(const void *registers);
+
+ bool validRegister(int num) const;
+ uint64_t getRegister(int num) const;
+ void setRegister(int num, uint64_t value);
+ bool validFloatRegister(int num) const;
+ double getFloatRegister(int num) const;
+ void setFloatRegister(int num, double value);
+ bool validVectorRegister(int num) const;
+ v128 getVectorRegister(int num) const;
+ void setVectorRegister(int num, v128 value);
+ const char *getRegisterName(int num);
+ void jumpto();
+ static int lastDwarfRegNum() { return 31; }
+
+ uint64_t getSP() const { return _registers.__o[6] + 2047; }
+ void setSP(uint64_t value) { _registers.__o[6] = value - 2047; }
+ uint64_t getIP() const { return _registers.__o[7]; }
+ void setIP(uint64_t value) { _registers.__o[7] = value; }
+ uint64_t getWCookie() const { return _wcookie; }
+
+private:
+ struct GPRs {
+ uint64_t __g[8];
+ uint64_t __o[8];
+ uint64_t __l[8];
+ uint64_t __i[8];
+ };
+
+ GPRs _registers;
+ uint64_t _wcookie;
+};
+
+inline Registers_sparc64::Registers_sparc64(const void *registers) {
+ static_assert((check_fit<Registers_sparc64, unw_context_t>::does_fit),
+ "sparc64 registers do not fit into unw_context_t");
+ memcpy(&_registers, static_cast<const uint8_t *>(registers),
+ sizeof(_registers));
+ memcpy(&_wcookie, static_cast<const uint8_t *>(registers) + sizeof(GPRs),
+ sizeof(_wcookie));
+}
+
+inline Registers_sparc64::Registers_sparc64() {
+ memset(&_registers, 0, sizeof(_registers));
+ _wcookie = 0;
+}
+
+inline bool Registers_sparc64::validRegister(int regNum) const {
+ if (regNum == UNW_REG_IP)
+ return true;
+ if (regNum == UNW_REG_SP)
+ return true;
+ if (regNum < 0)
+ return false;
+ if (regNum <= 31)
+ return true;
+ return false;
+}
+
+inline uint64_t Registers_sparc64::getRegister(int regNum) const {
+ if (regNum >= 0 && regNum <= 7)
+ return _registers.__g[regNum - 0];
+ if (regNum >= 8 && regNum <= 15)
+ return _registers.__o[regNum - 8];
+ if (regNum >= 16 && regNum <= 23)
+ return _registers.__l[regNum - 16];
+ if (regNum >= 24 && regNum <= 31)
+ return _registers.__i[regNum - 24];
+
+ switch (regNum) {
+ case UNW_REG_IP:
+ return _registers.__o[7];
+ case UNW_REG_SP:
+ return _registers.__o[6] + 2047;
+ }
+ _LIBUNWIND_ABORT("unsupported sparc64 register");
+}
+
+inline void Registers_sparc64::setRegister(int regNum, uint64_t value) {
+ if (regNum >= 0 && regNum <= 7) {
+ _registers.__g[regNum - 0] = value;
+ return;
+ }
+ if (regNum >= 8 && regNum <= 15) {
+ _registers.__o[regNum - 8] = value;
+ return;
+ }
+ if (regNum >= 16 && regNum <= 23) {
+ _registers.__l[regNum - 16] = value;
+ return;
+ }
+ if (regNum >= 24 && regNum <= 31) {
+ _registers.__i[regNum - 24] = value;
+ return;
+ }
+
+ switch (regNum) {
+ case UNW_REG_IP:
+ _registers.__o[7] = value;
+ return;
+ case UNW_REG_SP:
+ _registers.__o[6] = value - 2047;
+ return;
+ }
+ _LIBUNWIND_ABORT("unsupported sparc64 register");
+}
+
+inline bool Registers_sparc64::validFloatRegister(int) const {
+ return false;
+}
+
+inline double Registers_sparc64::getFloatRegister(int) const {
+ _LIBUNWIND_ABORT("no sparc64 float registers");
+}
+
+inline void Registers_sparc64::setFloatRegister(int, double) {
+ _LIBUNWIND_ABORT("no sparc64 float registers");
+}
+
+inline bool Registers_sparc64::validVectorRegister(int) const {
+ return false;
+}
+
+inline v128 Registers_sparc64::getVectorRegister(int) const {
+ _LIBUNWIND_ABORT("no sparc64 vector registers");
+}
+
+inline void Registers_sparc64::setVectorRegister(int, v128) {
+ _LIBUNWIND_ABORT("no sparc64 vector registers");
+}
+
+inline const char *Registers_sparc64::getRegisterName(int regNum) {
+ return "unknown register";
+}
+
+#endif // _LIBUNWIND_TARGET_SPARC64
} // namespace libunwind
#endif // __REGISTERS_HPP__
projects / openbsd / commitdiff