drm/i915/gt: Automate CCS Mode setting during engine resets

From Andi Shyti
be59b2d3d9750f784101d62cc0f25fb75e294f7e in linux-6.6.y/6.6.3
51c1b42a232f17743cd825be6790cb64735ff98f in mainline linux

diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c
index 044219c..99b71bb 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c
+++ b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c
@@ -8,14 +8,14 @@
 #include "intel_gt_ccs_mode.h"
 #include "intel_gt_regs.h"
 
-void intel_gt_apply_ccs_mode(struct intel_gt *gt)
+unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
 {
        int cslice;
        u32 mode = 0;
        int first_ccs = __ffs(CCS_MASK(gt));
 
        if (!IS_DG2(gt->i915))
-               return;
+               return 0;
 
        /* Build the value for the fixed CCS load balancing */
        for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
@@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt)
                                                     XEHP_CCS_MODE_CSLICE_MASK);
        }
 
-       intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
+       return mode;
 }

diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.h b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.h
index 9e5549c..55547f2 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.h
+++ b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.h
@@ -8,6 +8,6 @@
 
 struct intel_gt;
 
-void intel_gt_apply_ccs_mode(struct intel_gt *gt);
+unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt);
 
 #endif /* __INTEL_GT_CCS_MODE_H__ */

diff --git a/sys/dev/pci/drm/i915/gt/intel_workarounds.c b/sys/dev/pci/drm/i915/gt/intel_workarounds.c
index be060b3..8fbb068 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_workarounds.c
+++ b/sys/dev/pci/drm/i915/gt/intel_workarounds.c
@@ -2828,6 +2828,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
 static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
        struct intel_gt *gt = engine->gt;
+       u32 mode;
 
        if (!IS_DG2(gt->i915))
                return;
@@ -2844,7 +2845,8 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li
         * After having disabled automatic load balancing we need to
         * assign all slices to a single CCS. We will call it CCS mode 1
         */
-       intel_gt_apply_ccs_mode(gt);
+       mode = intel_gt_apply_ccs_mode(gt);
+       wa_masked_en(wal, XEHP_CCS_MODE, mode);
 }
 
 /*