-# $OpenBSD: Makefile,v 1.28 2020/04/10 22:26:46 kettenis Exp $
+# $OpenBSD: Makefile,v 1.29 2021/04/30 13:20:14 visa Exp $
MAN= agtimer.4 amdisplay.4 ampintc.4 amptimer.4 armliicc.4 \
cortex.4 cpsw.4 dmtimer.4 edma.4 gptimer.4 \
omap.4 omclock.4 omcm.4 omdog.4 omgpio.4 ommmc.4 omrng.4 omsysc.4 \
omwugen.4 prcm.4 \
sxie.4 sxiintc.4 \
- sxitimer.4 sxits.4 sysreg.4
+ sxitimer.4 sxits.4 sysreg.4 zqreset.4
MANSUBDIR=armv7
--- /dev/null
+.\" $OpenBSD: zqreset.4,v 1.1 2021/04/30 13:20:14 visa Exp $
+.\"
+.\" Copyright (c) 2021 Visa Hankala
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate: April 30 2021 $
+.Dt ZQRESET 4
+.Os
+.Sh NAME
+.Nm zqreset
+.Nd Xilinx Zynq-7000 reset controller
+.Sh SYNOPSIS
+.Cd "zqreset* at fdt?"
+.Sh DESCRIPTION
+The
+.Nm
+driver controls the reset signals for the integrated components
+of Zynq-7000 SoCs.
+.Sh SEE ALSO
+.Xr intro 4 ,
+.Xr zqclock 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 7.0 .
-# $OpenBSD: GENERIC,v 1.135 2021/04/24 07:49:11 visa Exp $
+# $OpenBSD: GENERIC,v 1.136 2021/04/30 13:20:14 visa Exp $
#
# For further information on compiling OpenBSD kernels, see the config(8)
# man page.
# Xilinx Zynq-7000
cduart* at fdt?
+zqreset* at fdt?
# I2C devices
abcrtc* at iic? # Abracon x80x RTC
-# $OpenBSD: RAMDISK,v 1.121 2021/04/24 07:49:11 visa Exp $
+# $OpenBSD: RAMDISK,v 1.122 2021/04/30 13:20:14 visa Exp $
machine armv7 arm
# Xilinx Zynq-7000
cduart* at fdt?
+zqreset* at fdt?
axppmic* at iic? # axp209 pmic
crosec* at iic?
-# $OpenBSD: files.armv7,v 1.37 2018/06/05 20:41:19 kettenis Exp $
+# $OpenBSD: files.armv7,v 1.38 2021/04/30 13:20:14 visa Exp $
maxpartitions 16
maxusers 2 8 64
include "arch/armv7/vexpress/files.vexpress"
include "arch/armv7/broadcom/files.broadcom"
include "arch/armv7/marvell/files.marvell"
+include "arch/armv7/xilinx/files.xilinx"
--- /dev/null
+# $OpenBSD: files.xilinx,v 1.1 2021/04/30 13:20:14 visa Exp $
+
+device zqreset
+attach zqreset at fdt
+file arch/armv7/xilinx/zqreset.c zqreset
--- /dev/null
+/* $OpenBSD: slcreg.h,v 1.1 2021/04/30 13:20:14 visa Exp $ */
+
+/*
+ * Copyright (c) 2021 Visa Hankala
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define SLCR_LOCK 0x0004
+#define SLCR_LOCK_KEY 0x767b
+#define SLCR_UNLOCK 0x0008
+#define SLCR_UNLOCK_KEY 0xdf0d
+#define SLCR_ARM_PLL_CTRL 0x0100
+#define SLCR_DDR_PLL_CTRL 0x0104
+#define SLCR_IO_PLL_CTRL 0x0108
+#define SLCR_PLL_CTRL_FDIV_MASK 0x7f
+#define SLCR_PLL_CTRL_FDIV_SHIFT 12
+#define SLCR_GEM0_CLK_CTRL 0x0140
+#define SLCR_GEM1_CLK_CTRL 0x0144
+#define SLCR_SDIO_CLK_CTRL 0x0150
+#define SLCR_UART_CLK_CTRL 0x0154
+#define SLCR_CLK_CTRL_DIVISOR1(x) (((x) >> 20) & 0x3f)
+#define SLCR_CLK_CTRL_DIVISOR1_SHIFT 20
+#define SLCR_CLK_CTRL_DIVISOR(x) (((x) >> 8) & 0x3f)
+#define SLCR_CLK_CTRL_DIVISOR_SHIFT 8
+#define SLCR_CLK_CTRL_SRCSEL_MASK (0x7 << 4)
+#define SLCR_CLK_CTRL_SRCSEL_DDR (0x3 << 4)
+#define SLCR_CLK_CTRL_SRCSEL_ARM (0x2 << 4)
+#define SLCR_CLK_CTRL_SRCSEL_IO (0x1 << 4)
+#define SLCR_CLK_CTRL_CLKACT(i) (0x1 << (i))
+#define SLCR_PSS_RST_CTRL 0x0200
+#define SLCR_PSS_RST_CTRL_SOFT_RST (1 << 0)
+
+#define SLCR_DIV_MASK 0x3f
+
+extern struct mutex zynq_slcr_lock;
+
+uint32_t zynq_slcr_read(struct regmap *, uint32_t);
+void zynq_slcr_write(struct regmap *, uint32_t, uint32_t);
--- /dev/null
+/* $OpenBSD: zqreset.c,v 1.1 2021/04/30 13:20:14 visa Exp $ */
+
+/*
+ * Copyright (c) 2021 Visa Hankala
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Xilinx Zynq-7000 reset controller.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/mutex.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+
+#include <dev/ofw/fdt.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_misc.h>
+
+#include <armv7/xilinx/slcreg.h>
+
+extern void (*cpuresetfn)(void);
+
+struct zqreset_softc {
+ struct device sc_dev;
+ struct regmap *sc_rm;
+};
+
+int zqreset_match(struct device *, void *, void *);
+void zqreset_attach(struct device *, struct device *, void *);
+
+void zqreset_cpureset(void);
+
+const struct cfattach zqreset_ca = {
+ sizeof(struct zqreset_softc), zqreset_match, zqreset_attach
+};
+
+struct cfdriver zqreset_cd = {
+ NULL, "zqreset", DV_DULL
+};
+
+struct zqreset_softc *zqreset_sc;
+
+struct mutex zynq_slcr_lock = MUTEX_INITIALIZER(IPL_HIGH);
+
+int
+zqreset_match(struct device *parent, void *match, void *aux)
+{
+ struct fdt_attach_args *faa = aux;
+
+ return OF_is_compatible(faa->fa_node, "xlnx,zynq-reset");
+}
+
+void
+zqreset_attach(struct device *parent, struct device *self, void *aux)
+{
+ struct fdt_attach_args *faa = aux;
+ struct zqreset_softc *sc = (struct zqreset_softc *)self;
+
+ sc->sc_rm = regmap_bynode(OF_parent(faa->fa_node));
+ if (sc->sc_rm == NULL) {
+ printf(": can't get regmap\n");
+ return;
+ }
+
+ printf("\n");
+
+ zqreset_sc = sc;
+ cpuresetfn = zqreset_cpureset;
+}
+
+void
+zqreset_cpureset(void)
+{
+ struct zqreset_softc *sc = zqreset_sc;
+
+ mtx_enter(&zynq_slcr_lock);
+ zynq_slcr_write(sc->sc_rm, SLCR_PSS_RST_CTRL,
+ SLCR_PSS_RST_CTRL_SOFT_RST);
+ mtx_leave(&zynq_slcr_lock);
+}
+
+uint32_t
+zynq_slcr_read(struct regmap *rm, uint32_t reg)
+{
+ return regmap_read_4(rm, reg);
+}
+
+void
+zynq_slcr_write(struct regmap *rm, uint32_t reg, uint32_t val)
+{
+ MUTEX_ASSERT_LOCKED(&zynq_slcr_lock);
+
+ regmap_write_4(rm, SLCR_UNLOCK, SLCR_UNLOCK_KEY);
+ regmap_write_4(rm, reg, val);
+ regmap_write_4(rm, SLCR_LOCK, SLCR_LOCK_KEY);
+}
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