-/* $OpenBSD: rkclock.c,v 1.85 2024/02/26 18:54:25 kettenis Exp $ */
+/* $OpenBSD: rkclock.c,v 1.86 2024/03/02 19:48:13 kettenis Exp $ */
/*
* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
*
SEL(13, 13), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
+ {
+ RK3588_CLK_SPI0, RK3588_CRU_CLKSEL_CON(59),
+ SEL(3, 2), 0,
+ { RK3588_CLK_200M_SRC, RK3588_CLK_150M_SRC, RK3588_XIN24M },
+ },
+ {
+ RK3588_CLK_SPI1, RK3588_CRU_CLKSEL_CON(59),
+ SEL(5, 4), 0,
+ { RK3588_CLK_200M_SRC, RK3588_CLK_150M_SRC, RK3588_XIN24M },
+ },
+ {
+ RK3588_CLK_SPI2, RK3588_CRU_CLKSEL_CON(59),
+ SEL(7, 6), 0,
+ { RK3588_CLK_200M_SRC, RK3588_CLK_150M_SRC, RK3588_XIN24M },
+ },
+ {
+ RK3588_CLK_SPI3, RK3588_CRU_CLKSEL_CON(59),
+ SEL(9, 8), 0,
+ { RK3588_CLK_200M_SRC, RK3588_CLK_150M_SRC, RK3588_XIN24M },
+ },
+ {
+ RK3588_CLK_SPI4, RK3588_CRU_CLKSEL_CON(59),
+ SEL(11, 10), 0,
+ { RK3588_CLK_200M_SRC, RK3588_CLK_150M_SRC, RK3588_XIN24M },
+ },
{
RK3588_CLK_UART1_SRC, RK3588_CRU_CLKSEL_CON(41),
SEL(14, 14), DIV(13, 9),
#define RK3588_CLK_I2C6 136
#define RK3588_CLK_I2C7 137
#define RK3588_CLK_I2C8 138
+#define RK3588_CLK_SPI0 151
+#define RK3588_CLK_SPI1 152
+#define RK3588_CLK_SPI2 153
+#define RK3588_CLK_SPI3 154
+#define RK3588_CLK_SPI4 155
#define RK3588_CLK_UART1_SRC 168
#define RK3588_CLK_UART1_FRAC 169
#define RK3588_CLK_UART1 170