-/* $OpenBSD: cpu.c,v 1.20 2014/11/16 12:30:56 deraadt Exp $ */
+/* $OpenBSD: cpu.c,v 1.21 2015/05/29 05:48:07 jsg Exp $ */
/* $NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $ */
generic_steppings },
{ CPU_ID_CORTEX_A15_R4, CPU_CLASS_ARMv7, "ARM Cortex A15 R4",
generic_steppings },
+ { CPU_ID_CORTEX_A17, CPU_CLASS_ARMv7, "ARM Cortex A17",
+ generic_steppings },
+ { CPU_ID_CORTEX_A17_R1, CPU_CLASS_ARMv7, "ARM Cortex A17 R1",
+ generic_steppings },
+ { CPU_ID_CORTEX_A53, CPU_CLASS_ARMv7, "ARM Cortex A53",
+ generic_steppings },
+ { CPU_ID_CORTEX_A53_R1, CPU_CLASS_ARMv7, "ARM Cortex A53 R1",
+ generic_steppings },
+ { CPU_ID_CORTEX_A57, CPU_CLASS_ARMv7, "ARM Cortex A57",
+ generic_steppings },
+ { CPU_ID_CORTEX_A57_R1, CPU_CLASS_ARMv7, "ARM Cortex A57 R1",
+ generic_steppings },
+ { CPU_ID_CORTEX_A72, CPU_CLASS_ARMv7, "ARM Cortex A72",
+ generic_steppings },
+ { CPU_ID_CORTEX_A72_R1, CPU_CLASS_ARMv7, "ARM Cortex A72 R1",
+ generic_steppings },
{ 0, CPU_CLASS_NONE, NULL, NULL }
};
-/* $OpenBSD: cpufunc.c,v 1.26 2014/04/03 10:17:34 mpi Exp $ */
+/* $OpenBSD: cpufunc.c,v 1.27 2015/05/29 05:48:07 jsg Exp $ */
/* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */
/*
(cputype & CPU_ID_CORTEX_A7_MASK) == CPU_ID_CORTEX_A7 ||
(cputype & CPU_ID_CORTEX_A8_MASK) == CPU_ID_CORTEX_A8 ||
(cputype & CPU_ID_CORTEX_A9_MASK) == CPU_ID_CORTEX_A9 ||
- (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15) {
+ (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15 ||
+ (cputype & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17) {
cpufuncs = armv7_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
arm_get_cachetype_cp15v7();
-/* $OpenBSD: agtimer.c,v 1.2 2015/05/29 02:35:43 jsg Exp $ */
+/* $OpenBSD: agtimer.c,v 1.3 2015/05/29 05:48:07 jsg Exp $ */
/*
* Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
* Copyright (c) 2013 Patrick Wildt <patrick@blueri.se>
agtimer_match(struct device *parent, void *cfdata, void *aux)
{
if ((cpufunc_id() & CPU_ID_CORTEX_A7_MASK) == CPU_ID_CORTEX_A7 ||
- (cpufunc_id() & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15)
+ (cpufunc_id() & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15 ||
+ (cpufunc_id() & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17)
return (1);
return 0;
-/* $OpenBSD: ampintc.c,v 1.5 2014/12/13 21:05:32 doug Exp $ */
+/* $OpenBSD: ampintc.c,v 1.6 2015/05/29 05:48:07 jsg Exp $ */
/*
* Copyright (c) 2007,2009,2011 Dale Rahn <drahn@openbsd.org>
*
icdsize = ICD_SIZE;
if ((cputype & CPU_ID_CORTEX_A7_MASK) == CPU_ID_CORTEX_A7 ||
- (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15) {
+ (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15 ||
+ (cputype & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17) {
icp = ia->ca_periphbase + ICP_A7_A15_ADDR;
icpsize = ICP_A7_A15_SIZE;
icd = ia->ca_periphbase + ICD_A7_A15_ADDR;
-/* $OpenBSD: cortex.c,v 1.2 2013/08/06 14:21:13 patrick Exp $ */
+/* $OpenBSD: cortex.c,v 1.3 2015/05/29 05:48:07 jsg Exp $ */
/* $NetBSD: mainbus.c,v 1.3 2001/06/13 17:52:43 nathanw Exp $ */
/*
if ((cputype & CPU_ID_CORTEX_A7_MASK) == CPU_ID_CORTEX_A7 ||
(cputype & CPU_ID_CORTEX_A9_MASK) == CPU_ID_CORTEX_A9 ||
- (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15) {
+ (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15 ||
+ (cputype & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17) {
if (armv7_periphbase())
return (1);
}
-/* $OpenBSD: armreg.h,v 1.15 2015/01/17 08:00:41 jsg Exp $ */
+/* $OpenBSD: armreg.h,v 1.16 2015/05/29 05:48:07 jsg Exp $ */
/* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */
/*
#define CPU_ID_CORTEX_A15_R3 0x413fc0f0
#define CPU_ID_CORTEX_A15_R4 0x414fc0f0
#define CPU_ID_CORTEX_A15_MASK 0xff0ffff0
-
+#define CPU_ID_CORTEX_A17 0x410fc0e0
+#define CPU_ID_CORTEX_A17_R1 0x411fc0e0
+#define CPU_ID_CORTEX_A17_MASK 0xff0ffff0
+#define CPU_ID_CORTEX_A53 0x410fd030
+#define CPU_ID_CORTEX_A53_R1 0x411fd030
+#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0
+#define CPU_ID_CORTEX_A57 0x410fd070
+#define CPU_ID_CORTEX_A57_R1 0x411fd070
+#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0
+#define CPU_ID_CORTEX_A72 0x410fd080
+#define CPU_ID_CORTEX_A72_R1 0x411fd080
+#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0
/* ARM3-specific coprocessor 15 registers */
#define ARM3_CP15_FLUSH 1