drm/amd/display: reset dcn31 SMU mailbox on failures

From Mario Limonciello
f71c91ed1d4b4bfbbb55327b04dcc32b2d970f62 in linux 5.15.y/5.15.18
83293f7f3d15fc56e86bd5067a2c88b6b233ac3a in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index f7f58d4..2bfa13e 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -119,6 +119,12 @@ int dcn31_smu_send_msg_with_param(
 
        result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
 
+       if (result == VBIOSSMC_Result_Failed) {
+               ASSERT(0);
+               REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
+               return -1;
+       }
+
        if (IS_SMU_TIMEOUT(result)) {
                ASSERT(0);
                dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);