drm/amd/display: limit timing for single dimm memory

From Daniel Miess
2abff94db2c6d692772fc07f39b4f9ee894c7197 in linux-6.1.y/6.1.28
1e994cc0956b8dabd1b1fef315bbd722733b8aa8 in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c
index 2f9c6d6..ffaa4e5 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1689,6 +1689,23 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi
        *panel_config = panel_config_defaults;
 }
 
+static bool filter_modes_for_single_channel_workaround(struct dc *dc,
+               struct dc_state *context)
+{
+       // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
+       if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) {
+               int total_phy_pix_clk = 0;
+
+               for (int i = 0; i < context->stream_count; i++)
+                       if (context->res_ctx.pipe_ctx[i].stream)
+                               total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
+
+               if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
+                       return true;
+       }
+       return false;
+}
+
 bool dcn314_validate_bandwidth(struct dc *dc,
                struct dc_state *context,
                bool fast_validate)
@@ -1704,6 +1721,9 @@ bool dcn314_validate_bandwidth(struct dc *dc,
 
        BW_VAL_TRACE_COUNT();
 
+       if (filter_modes_for_single_channel_workaround(dc, context))
+               goto validate_fail;
+
        DC_FP_START();
        // do not support self refresh only
        out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);