drm/i915/mtl: Add Wa_14019821291

From Dnyaneshwar Bhadane
43dea469e99b10ecc967a3576e50a5d416daf13c in mainline linux

diff --git a/sys/dev/pci/drm/i915/gem/i915_gem_stolen.c b/sys/dev/pci/drm/i915/gem/i915_gem_stolen.c
index 0c9dc66..b02b902 100644 (file)
--- a/sys/dev/pci/drm/i915/gem/i915_gem_stolen.c
+++ b/sys/dev/pci/drm/i915/gem/i915_gem_stolen.c
@@ -388,6 +388,27 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
 
        drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
 
+       /* Wa_14019821291 */
+       if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
+               /*
+                * This workaround is primarily implemented by the BIOS.  We
+                * just need to figure out whether the BIOS has applied the
+                * workaround (meaning the programmed address falls within
+                * the DSM) and, if so, reserve that part of the DSM to
+                * prevent accidental reuse.  The DSM location should be just
+                * below the WOPCM.
+                */
+               u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,
+                                                           MTL_GSCPSMI_BASEADDR_LSB,
+                                                           MTL_GSCPSMI_BASEADDR_MSB);
+               if (gscpsmi_base >= i915->dsm.stolen.start &&
+                   gscpsmi_base < i915->dsm.stolen.end) {
+                       *base = gscpsmi_base;
+                       *size = i915->dsm.stolen.end - gscpsmi_base;
+                       return;
+               }
+       }
+
        switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
        case GEN8_STOLEN_RESERVED_1M:
                *size = 1024 * 1024;

diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_regs.h b/sys/dev/pci/drm/i915/gt/intel_gt_regs.h
index 64acab1..64dca60 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_gt_regs.h
+++ b/sys/dev/pci/drm/i915/gt/intel_gt_regs.h
@@ -538,6 +538,9 @@
 #define XEHP_SQCM                              MCR_REG(0x8724)
 #define   EN_32B_ACCESS                                REG_BIT(30)
 
+#define MTL_GSCPSMI_BASEADDR_LSB               _MMIO(0x880c)
+#define MTL_GSCPSMI_BASEADDR_MSB               _MMIO(0x8810)
+
 #define HSW_IDICR                              _MMIO(0x9008)
 #define   IDIHASHMSK(x)                                (((x) & 0x3f) << 16)