-/* $OpenBSD: amd64errata.c,v 1.10 2022/09/20 07:54:27 jsg Exp $ */
+/* $OpenBSD: amd64errata.c,v 1.11 2022/09/22 04:36:37 robert Exp $ */
/* $NetBSD: errata.c,v 1.6 2007/02/05 21:05:45 ad Exp $ */
/*-
#include <machine/cpufunc.h>
#include <machine/specialreg.h>
-
typedef struct errata {
u_short e_num;
u_short e_reported;
int rc;
int found = 0;
int corrected = 0;
+ static int printed = 0;
CPUID(0x80000001, code, dummy, dummy, dummy);
int first = 1;
/* Print out found and corrected */
- printf("%s: AMD %s", ci->ci_dev->dv_xname,
- (corrected == 1) ? "erratum" : "errata");
+ if (!printed) {
+ printf("%s: AMD %s", ci->ci_dev->dv_xname,
+ (corrected == 1) ? "erratum" : "errata");
+ }
for (e = errata; e < ex; e++) {
if (e->e_reported == 2) {
- if (! first)
- printf(",");
- printf(" %d", e->e_num);
+ if (!printed) {
+ if (! first)
+ printf(",");
+ printf(" %d", e->e_num);
+ }
first = 0;
}
}
- printf(" detected and fixed\n");
+ if (!printed)
+ printf(" detected and fixed\n");
}
#endif
int first = 1;
/* Print out found but not corrected */
- printf("%s: AMD %s", ci->ci_dev->dv_xname,
- (found == 1) ? "erratum" : "errata");
+ if (!printed) {
+ printf("%s: AMD %s", ci->ci_dev->dv_xname,
+ (found == 1) ? "erratum" : "errata");
+ }
for (e = errata; e < ex; e++) {
if (e->e_reported == 1) {
- if (! first)
- printf(",");
- printf(" %d", e->e_num);
+ if (!printed) {
+ if (! first)
+ printf(",");
+ printf(" %d", e->e_num);
+ }
first = 0;
}
}
- printf(" present, BIOS upgrade may be required\n");
+ if (!printed)
+ printf(" present, BIOS upgrade may be required\n");
}
+
+ /* Print only one time for the first CPU */
+ printed = 1;
}
-/* $OpenBSD: cpu.c,v 1.160 2022/09/20 14:28:27 robert Exp $ */
+/* $OpenBSD: cpu.c,v 1.161 2022/09/22 04:36:37 robert Exp $ */
/* $NetBSD: cpu.c,v 1.1 2003/04/26 18:39:26 fvdl Exp $ */
/*-
}
}
- /*
- * "Mitigation G-2" per AMD's Whitepaper "Software Techniques
- * for Managing Speculation on AMD Processors"
- *
- * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch
- * serializing instruction.
- *
- * This MSR is available on all AMD families >= 10h, except 11h
- * where LFENCE is always serializing.
- */
if (!strcmp(cpu_vendor, "AuthenticAMD")) {
+ /* Apply AMD errata */
+ amd64_errata(ci);
+
+ /*
+ * "Mitigation G-2" per AMD's Whitepaper "Software Techniques
+ * for Managing Speculation on AMD Processors"
+ *
+ * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch
+ * serializing instruction.
+ *
+ * This MSR is available on all AMD families >= 10h, except 11h
+ * where LFENCE is always serializing.
+ */
if (family >= 0x10 && family != 0x11) {
msr = rdmsr(MSR_DE_CFG);
if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) {
-/* $OpenBSD: identcpu.c,v 1.128 2022/09/20 14:28:27 robert Exp $ */
+/* $OpenBSD: identcpu.c,v 1.129 2022/09/22 04:36:38 robert Exp $ */
/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */
/*
}
#endif
- if (!strcmp(cpu_vendor, "AuthenticAMD"))
- amd64_errata(ci);
-
if (CPU_IS_PRIMARY(ci) && !strcmp(cpu_vendor, "CentaurHauls")) {
ci->cpu_setup = via_nano_setup;
#ifndef SMALL_KERNEL