Add RK356x TSADC clocks.

ok patrick@

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index 5154b26..ef0a6e9 100644 (file)
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: rkclock.c,v 1.63 2022/10/09 20:31:30 kettenis Exp $   */
+/*     $OpenBSD: rkclock.c,v 1.64 2023/02/13 19:19:29 kettenis Exp $   */
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -3017,6 +3017,16 @@ const struct rkclock rk3568_clocks[] = {
                { RK3568_XIN24M, RK3568_GPLL_400M, RK3568_GPLL_300M,
                  RK3568_CPLL_100M, RK3568_CPLL_50M, RK3568_CLK_OSC0_DIV_750K }
        },
+       {
+               RK3568_CLK_TSADC_TSEN, RK3568_CRU_CLKSEL_CON(51),
+               SEL(5, 4), DIV(2, 0),
+               { RK3568_XIN24M, RK3568_GPLL_100M, RK3568_CPLL_100M }
+       },
+       {
+               RK3568_CLK_TSADC, RK3568_CRU_CLKSEL_CON(51),
+               0, DIV(14, 8),
+               { RK3568_CLK_TSADC_TSEN }
+       },
        {
                RK3568_SCLK_UART1, RK3568_CRU_CLKSEL_CON(52),
                SEL(13, 12), 0,
@@ -3107,6 +3117,11 @@ const struct rkclock rk3568_clocks[] = {
                0, DIV(12, 8),
                { RK3568_PLL_GPLL }
        },
+       {
+               RK3568_GPLL_100M, RK3568_CRU_CLKSEL_CON(77),
+               0, DIV(4, 0),
+               { RK3568_PLL_GPLL }
+       },
        {
                RK3568_CLK_OSC0_DIV_750K, RK3568_CRU_CLKSEL_CON(82),
                0, DIV(13, 8),

diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 9ac62ee..15ba3dc 100644 (file)
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -285,6 +285,8 @@
 
 #define RK3568_CLK_SDMMC0              177
 #define RK3568_CLK_SDMMC1              179
+#define RK3568_CLK_TSADC_TSEN          272
+#define RK3568_CLK_TSADC               273
 #define RK3568_SCLK_UART1              287
 #define RK3568_SCLK_UART2              291
 #define RK3568_SCLK_UART3              295
@@ -304,8 +306,9 @@
 #define RK3568_CPLL_50M                        415
 #define RK3568_CPLL_100M               417
 
-#define RK3568_GPLL_400M               1020
-#define RK3568_GPLL_300M               1021
+#define RK3568_GPLL_400M               1019
+#define RK3568_GPLL_300M               1020
+#define RK3568_GPLL_100M               1021
 #define RK3568_CLK_OSC0_DIV_750K       1022
 #define RK3568_XIN24M                  1023