drm/i915: Add Wa_14015150844

From Shekhar Chauhan
4632e3209f4b4349ebe67597897045b1a8af9daa in mainline linux

diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_regs.h b/sys/dev/pci/drm/i915/gt/intel_gt_regs.h
index 9e147ea..11644bf 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_gt_regs.h
+++ b/sys/dev/pci/drm/i915/gt/intel_gt_regs.h
@@ -1227,6 +1227,8 @@
 
 #define XEHP_HDC_CHICKEN0                      MCR_REG(0xe5f0)
 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK       REG_GENMASK(13, 11)
+#define   DIS_ATOMIC_CHAINING_TYPED_WRITES     REG_BIT(3)
+
 #define ICL_HDC_MODE                           MCR_REG(0xe5f4)
 
 #define EU_PERF_CNTL2                          PERF_REG(0xe658)

diff --git a/sys/dev/pci/drm/i915/gt/intel_workarounds.c b/sys/dev/pci/drm/i915/gt/intel_workarounds.c
index f804801..bb94f66 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_workarounds.c
+++ b/sys/dev/pci/drm/i915/gt/intel_workarounds.c
@@ -2344,6 +2344,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                                  LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
        }
 
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
+           IS_DG2(i915)) {
+               /* Wa_14015150844 */
+               wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0,
+                          _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),
+                          0, true);
+       }
+
        if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) {
                /* Wa_22014600077:dg2 */
                wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,