--- /dev/null
+# $OpenBSD: Makefile,v 1.1 2021/04/29 05:32:01 drahn Exp $
+
+.include <bsd.own.mk>
+
+LLVM_SRCS= ${.CURDIR}/../../../../../llvm/llvm
+
+HDRS= RISCVGenAsmMatcher.inc RISCVGenAsmWriter.inc \
+ RISCVGenCallingConv.inc RISCVGenDAGISel.inc \
+ RISCVGenDisassemblerTables.inc \
+ RISCVGenInstrInfo.inc RISCVGenRegisterInfo.inc \
+ RISCVGenSubtargetInfo.inc \
+ RISCVGenMCCodeEmitter.inc RISCVGenMCPseudoLowering.inc \
+ RISCVGenSystemOperands.inc RISCVGenRegisterBank.inc \
+ RISCVGenGlobalISel.inc RISCVGenCompressInstEmitter.inc
+
+# RISCVGenGICombiner.inc RISCVGenFastISel.inc
+
+all: ${HDRS}
+
+install:
+ @# Nothing here so far ...
+
+clean cleandir:
+ rm -f ${HDRS}
+
+RISCVGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
+ -I${LLVM_SRCS}/include \
+ -I${LLVM_SRCS}/lib/Target/RISCV -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenFastISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-fast-isel \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenSystemOperands.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenCompressInstEmitter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen --gen-compress-inst-emitter \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+RISCVGenGICombiner.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
+ ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
+ -combiners="RISCVPreLegalizerCombinerHelper" \
+ -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
+ -o ${.TARGET} ${.ALLSRC}
+
+.include <bsd.obj.mk>
--- /dev/null
+//===- llvm-build generated file --------------------------------*- C++ -*-===//
+//
+// Component Library Dependency Table
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+struct AvailableComponent {
+ /// The name of the component.
+ const char *Name;
+
+ /// The name of the library for this component (or NULL).
+ const char *Library;
+
+ /// Whether the component is installed.
+ bool IsInstalled;
+
+ /// The list of libraries required when linking this component.
+ const char *RequiredLibraries[25];
+} AvailableComponents[84] = {
+ { "aggressiveinstcombine", "LLVMAggressiveInstCombine", true, { "analysis", "core", "support", "transformutils" } },
+ { "all", nullptr, true, { "all-targets", "coroutines", "coverage", "debuginfogsym", "dlltooldriver", "dwarflinker", "engine", "frontendopenmp", "fuzzmutate", "gtest_main", "libdriver", "lineeditor", "lto", "mca", "mcjit", "native", "nativecodegen", "objectyaml", "orcjit", "symbolize", "tablegen", "testingsupport", "windowsmanifest", "xray" } },
+ { "all-targets", nullptr, true, { "amdgpu", "riscv" } },
+ { "amdgpu", nullptr, true, { "amdgpuinfo", "amdgpuutils", "amdgpudesc", "amdgpuasmparser", "amdgpucodegen", "amdgpudisassembler" } },
+ { "amdgpuasmparser", "LLVMAMDGPUAsmParser", true, { "mc", "mcparser", "amdgpudesc", "amdgpuinfo", "amdgpuutils", "support" } },
+ { "amdgpucodegen", "LLVMAMDGPUCodeGen", true, { "analysis", "asmprinter", "codegen", "core", "ipo", "mc", "amdgpudesc", "amdgpuinfo", "amdgpuutils", "scalaropts", "selectiondag", "support", "target", "transformutils", "vectorize", "globalisel", "binaryformat", "mirparser" } },
+ { "amdgpudesc", "LLVMAMDGPUDesc", true, { "core", "mc", "amdgpuinfo", "amdgpuutils", "support", "binaryformat" } },
+ { "amdgpudisassembler", "LLVMAMDGPUDisassembler", true, { "amdgpudesc", "amdgpuinfo", "amdgpuutils", "mc", "mcdisassembler", "support" } },
+ { "amdgpuinfo", "LLVMAMDGPUInfo", true, { "support" } },
+ { "amdgpuutils", "LLVMAMDGPUUtils", true, { "core", "mc", "binaryformat", "support" } },
+ { "analysis", "LLVMAnalysis", true, { "binaryformat", "core", "object", "profiledata", "support" } },
+ { "asmparser", "LLVMAsmParser", true, { "binaryformat", "core", "support" } },
+ { "asmprinter", "LLVMAsmPrinter", true, { "analysis", "binaryformat", "codegen", "core", "debuginfocodeview", "debuginfodwarf", "debuginfomsf", "mc", "mcparser", "remarks", "support", "target" } },
+ { "binaryformat", "LLVMBinaryFormat", true, { "support" } },
+ { "bitreader", "LLVMBitReader", true, { "bitstreamreader", "core", "support" } },
+ { "bitstreamreader", "LLVMBitstreamReader", true, { "support" } },
+ { "bitwriter", "LLVMBitWriter", true, { "analysis", "core", "mc", "object", "support" } },
+ { "cfguard", "LLVMCFGuard", true, { "core", "support" } },
+ { "codegen", "LLVMCodeGen", true, { "analysis", "bitreader", "bitwriter", "core", "mc", "profiledata", "scalaropts", "support", "target", "transformutils" } },
+ { "core", "LLVMCore", true, { "binaryformat", "remarks", "support" } },
+ { "coroutines", "LLVMCoroutines", true, { "analysis", "core", "ipo", "scalaropts", "support", "transformutils" } },
+ { "coverage", "LLVMCoverage", true, { "core", "object", "profiledata", "support" } },
+ { "debuginfocodeview", "LLVMDebugInfoCodeView", true, { "support", "debuginfomsf" } },
+ { "debuginfodwarf", "LLVMDebugInfoDWARF", true, { "binaryformat", "object", "mc", "support" } },
+ { "debuginfogsym", "LLVMDebugInfoGSYM", true, { "mc", "support" } },
+ { "debuginfomsf", "LLVMDebugInfoMSF", true, { "support" } },
+ { "debuginfopdb", "LLVMDebugInfoPDB", true, { "object", "support", "debuginfocodeview", "debuginfomsf" } },
+ { "demangle", "LLVMDemangle", true, { } },
+ { "dlltooldriver", "LLVMDlltoolDriver", true, { "object", "option", "support" } },
+ { "dwarflinker", "LLVMDWARFLinker", true, { "debuginfodwarf", "asmprinter", "codegen", "mc", "object", "support" } },
+ { "engine", nullptr, true, { "interpreter" } },
+ { "executionengine", "LLVMExecutionEngine", true, { "core", "mc", "object", "runtimedyld", "support", "target" } },
+ { "frontendopenmp", "LLVMFrontendOpenMP", true, { "core", "support", "transformutils" } },
+ { "fuzzmutate", "LLVMFuzzMutate", true, { "analysis", "bitreader", "bitwriter", "core", "scalaropts", "support", "target" } },
+ { "globalisel", "LLVMGlobalISel", true, { "analysis", "codegen", "core", "mc", "selectiondag", "support", "target", "transformutils" } },
+ { "gtest", "gtest", false, { "support" } },
+ { "gtest_main", "gtest_main", false, { "gtest" } },
+ { "instcombine", "LLVMInstCombine", true, { "analysis", "core", "support", "transformutils" } },
+ { "instrumentation", "LLVMInstrumentation", true, { "analysis", "core", "mc", "support", "transformutils", "profiledata" } },
+ { "interpreter", "LLVMInterpreter", true, { "codegen", "core", "executionengine", "support" } },
+ { "ipo", "LLVMipo", true, { "aggressiveinstcombine", "analysis", "bitreader", "bitwriter", "core", "instcombine", "irreader", "linker", "object", "profiledata", "scalaropts", "support", "transformutils", "vectorize", "instrumentation" } },
+ { "irreader", "LLVMIRReader", true, { "asmparser", "bitreader", "core", "support" } },
+ { "jitlink", "LLVMJITLink", true, { "binaryformat", "object", "support" } },
+ { "libdriver", "LLVMLibDriver", true, { "binaryformat", "bitreader", "object", "option", "support" } },
+ { "lineeditor", "LLVMLineEditor", true, { "support" } },
+ { "linker", "LLVMLinker", true, { "core", "support", "transformutils" } },
+ { "lto", "LLVMLTO", true, { "aggressiveinstcombine", "analysis", "bitreader", "bitwriter", "codegen", "core", "ipo", "instcombine", "linker", "mc", "objcarcopts", "object", "passes", "remarks", "scalaropts", "support", "target", "transformutils" } },
+ { "mc", "LLVMMC", true, { "support", "binaryformat", "debuginfocodeview" } },
+ { "mca", "LLVMMCA", true, { "mc", "support" } },
+ { "mcdisassembler", "LLVMMCDisassembler", true, { "mc", "support" } },
+ { "mcjit", "LLVMMCJIT", true, { "core", "executionengine", "object", "runtimedyld", "support", "target" } },
+ { "mcparser", "LLVMMCParser", true, { "mc", "support" } },
+ { "mirparser", "LLVMMIRParser", true, { "asmparser", "binaryformat", "codegen", "core", "mc", "support", "target" } },
+ { "native", nullptr, true, { } },
+ { "nativecodegen", nullptr, true, { } },
+ { "objcarcopts", "LLVMObjCARCOpts", true, { "analysis", "core", "support", "transformutils" } },
+ { "object", "LLVMObject", true, { "bitreader", "core", "mc", "binaryformat", "mcparser", "support", "textapi" } },
+ { "objectyaml", "LLVMObjectYAML", true, { "object", "support", "debuginfocodeview", "mc" } },
+ { "option", "LLVMOption", true, { "support" } },
+ { "orcerror", "LLVMOrcError", true, { "support" } },
+ { "orcjit", "LLVMOrcJIT", true, { "core", "executionengine", "jitlink", "object", "orcerror", "mc", "passes", "runtimedyld", "support", "target", "transformutils" } },
+ { "passes", "LLVMPasses", true, { "aggressiveinstcombine", "analysis", "codegen", "core", "ipo", "instcombine", "scalaropts", "support", "target", "transformutils", "vectorize", "instrumentation" } },
+ { "profiledata", "LLVMProfileData", true, { "core", "support" } },
+ { "remarks", "LLVMRemarks", true, { "bitstreamreader", "support" } },
+ { "riscv", nullptr, true, { "riscvinfo", "riscvutils", "riscvdesc", "riscvasmparser", "riscvcodegen", "riscvdisassembler" } },
+ { "riscvasmparser", "LLVMRISCVAsmParser", true, { "mc", "mcparser", "riscvdesc", "riscvinfo", "riscvutils", "support" } },
+ { "riscvcodegen", "LLVMRISCVCodeGen", true, { "analysis", "asmprinter", "core", "codegen", "mc", "riscvdesc", "riscvinfo", "riscvutils", "selectiondag", "support", "target", "globalisel" } },
+ { "riscvdesc", "LLVMRISCVDesc", true, { "mc", "riscvinfo", "riscvutils", "support" } },
+ { "riscvdisassembler", "LLVMRISCVDisassembler", true, { "mcdisassembler", "riscvinfo", "support" } },
+ { "riscvinfo", "LLVMRISCVInfo", true, { "support" } },
+ { "riscvutils", "LLVMRISCVUtils", true, { "support" } },
+ { "runtimedyld", "LLVMRuntimeDyld", true, { "mc", "object", "support" } },
+ { "scalaropts", "LLVMScalarOpts", true, { "aggressiveinstcombine", "analysis", "core", "instcombine", "support", "transformutils" } },
+ { "selectiondag", "LLVMSelectionDAG", true, { "analysis", "codegen", "core", "mc", "support", "target", "transformutils" } },
+ { "support", "LLVMSupport", true, { "demangle" } },
+ { "symbolize", "LLVMSymbolize", true, { "debuginfodwarf", "debuginfopdb", "object", "support", "demangle" } },
+ { "tablegen", "LLVMTableGen", true, { "support" } },
+ { "target", "LLVMTarget", true, { "analysis", "core", "mc", "support" } },
+ { "testingsupport", "LLVMTestingSupport", false, { "support" } },
+ { "textapi", "LLVMTextAPI", true, { "support", "binaryformat" } },
+ { "transformutils", "LLVMTransformUtils", true, { "analysis", "core", "support" } },
+ { "vectorize", "LLVMVectorize", true, { "analysis", "core", "support", "transformutils" } },
+ { "windowsmanifest", "LLVMWindowsManifest", true, { "support" } },
+ { "xray", "LLVMXRay", true, { "support", "object" } },
+};