-/* $OpenBSD: rkclock.c,v 1.79 2023/07/07 16:52:57 patrick Exp $ */
+/* $OpenBSD: rkclock.c,v 1.80 2023/07/07 16:53:39 patrick Exp $ */
/*
* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
*
{ RK3588_CLK_PMU1_400M_SRC, RK3588_CLK_PMU1_200M_SRC,
RK3588_CLK_PMU1_100M_SRC, RK3588_XIN24M }
},
+ {
+ RK3588_CLK_PMU1PWM, RK3588_PMUCRU_CLKSEL_CON(2),
+ SEL(10, 9), 0,
+ { RK3588_CLK_PMU1_100M_SRC, RK3588_CLK_PMU1_50M_SRC,
+ RK3588_XIN24M }
+ },
{
RK3588_CLK_UART0_SRC, RK3588_PMUCRU_CLKSEL_CON(3),
0, DIV(11, 7),
#define RK3588_PCLK_PMU1_ROOT 645
#define RK3588_PCLK_PMU0_ROOT 646
#define RK3588_HCLK_PMU_CM0_ROOT 647
+#define RK3588_CLK_PMU1PWM 658
#define RK3588_CLK_UART0_SRC 664
#define RK3588_CLK_UART0_FRAC 665
#define RK3588_CLK_UART0 666