perusing drivers on other systems, there appears to be some cynism about

how this chip comes out of D3 and when the RESET register is touched.
Some systems were still wasn't resuming reliabily, but adding these
delays has eliminated resume-hangs.
ok kettenis mlarkin

diff --git a/sys/dev/pci/dwiic_pci.c b/sys/dev/pci/dwiic_pci.c
index 3d3548c..c93649f 100644 (file)
--- a/sys/dev/pci/dwiic_pci.c
+++ b/sys/dev/pci/dwiic_pci.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: dwiic_pci.c,v 1.29 2024/08/17 02:24:06 deraadt Exp $ */
+/* $OpenBSD: dwiic_pci.c,v 1.30 2024/08/17 02:31:15 deraadt Exp $ */
 /*
  * Synopsys DesignWare I2C controller
  * PCI attachment
@@ -294,8 +294,10 @@ dwiic_pci_activate(struct device *self, int act)
 
        switch (act) {
        case DVACT_RESUME:
+               DELAY(10000);   /* 10 msec */
                bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPSS_RESETS,
                    (LPSS_RESETS_I2C | LPSS_RESETS_IDMA));
+               DELAY(10000);   /* 10 msec */
                break;
        }
        return dwiic_activate(self, act);