drm/amd/display: fix seamless odm transitions

From Dmytro Laktyushkin
31fb25ecbba6ebe11dc497952310b986e05dd3a0 in linux-6.1.y/6.1.40
75c2b7ed080d7421157c03064be82275364136e7 in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 2d49e99..622efa5 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1678,6 +1678,17 @@ static void dcn20_program_pipe(
 
                if (hws->funcs.setup_vupdate_interrupt)
                        hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+
+               if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
+                       unsigned int k1_div, k2_div;
+
+                       hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
+
+                       dc->res_pool->dccg->funcs->set_pixel_rate_div(
+                               dc->res_pool->dccg,
+                               pipe_ctx->stream_res.tg->inst,
+                               k1_div, k2_div);
+               }
        }
 
        if (pipe_ctx->update_flags.bits.odm)

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.c b/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.c
index 2b33eeb..fe941b1 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -98,7 +98,7 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i
        optc1->opp_count = opp_cnt;
 }
 
-static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
+void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.h b/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.h
index 5e57c39..e5c5343 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.h
+++ b/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.h
@@ -250,5 +250,6 @@
        SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 
 void dcn32_timing_generator_init(struct optc *optc1);
+void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
 
 #endif /* __DC_OPTC_DCN32_H__ */