drop detection code for 386sx/386dx CPUs

OpenBSD/i386 doesn't actually support running on 386sx or 386dx CPUs
so we don't need to test whether we're running on one of these CPUs
anymore.

The 486 (which was launched in 1989) added a few new features over
the 386:
- an alignment check flag in EFLAGS
- 3 new userland instructions: bswap / cmpxchg / xadd
- 3 new kernel mode instructions: invd / wbinvd / invlpg
- new bits in CR0 (386 CPUs did not support ring0 write protection)
- new bits in CR3

In this diff, we remove the code that checks for the alignment check
flag as we've only supported Pentium (or newer) CPUs for some time.

The rest of the diff is about updating comments related to pre-486
CPUs. 2 files under arch/amd64 are updated to keep them in sync
with the arch/i386 updates.

ok mlarkin@, jsg@; tweak from miod@

diff --git a/sys/arch/amd64/amd64/lapic.c b/sys/arch/amd64/amd64/lapic.c
index a94689b..e823655 100644 (file)
--- a/sys/arch/amd64/amd64/lapic.c
+++ b/sys/arch/amd64/amd64/lapic.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: lapic.c,v 1.59 2021/08/31 15:53:36 patrick Exp $      */
+/*     $OpenBSD: lapic.c,v 1.60 2022/08/15 04:17:50 daniel Exp $       */
 /* $NetBSD: lapic.c,v 1.2 2003/05/08 01:04:35 fvdl Exp $ */
 
 /*-
@@ -213,9 +213,7 @@ lapic_map(paddr_t lapic_base)
                va = (vaddr_t)&local_apic;
        } else {
                /*
-                * Map local apic.  If we have a local apic, it's safe to
-                * assume we're on a 486 or better and can use invlpg and
-                * non-cacheable PTEs
+                * Map local apic.
                 *
                 * Whap the PTE "by hand" rather than calling pmap_kenter_pa
                 * because the latter will attempt to invoke TLB shootdown

diff --git a/sys/arch/amd64/stand/mbr/mbr.S b/sys/arch/amd64/stand/mbr/mbr.S
index 8099532..6fd9e6a 100644 (file)
--- a/sys/arch/amd64/stand/mbr/mbr.S
+++ b/sys/arch/amd64/stand/mbr/mbr.S
@@ -1,4 +1,4 @@
-/*     $OpenBSD: mbr.S,v 1.7 2022/06/27 16:10:09 deraadt Exp $ */
+/*     $OpenBSD: mbr.S,v 1.8 2022/08/15 04:17:50 daniel Exp $  */
 
 /*
  * Copyright (c) 1997 Michael Shalayeff and Tobias Weingartner
@@ -112,7 +112,7 @@ start:
         *
         * Accordingly, this code will fail on very early 8086/88s, but
         * nick@ will just have to live with it.  Others will note that
-        * we require an 80386 (or compatible) or above processor, anyway.
+        * we require at least a Pentium compatible processor anyway.
         */
        /* cli */
        movw    %ax, %ss

diff --git a/sys/arch/i386/i386/cpu.c b/sys/arch/i386/i386/cpu.c
index 772dafa..9916865 100644 (file)
--- a/sys/arch/i386/i386/cpu.c
+++ b/sys/arch/i386/i386/cpu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: cpu.c,v 1.108 2022/02/21 10:24:28 mpi Exp $   */
+/*     $OpenBSD: cpu.c,v 1.109 2022/08/15 04:17:50 daniel Exp $        */
 /* $NetBSD: cpu.c,v 1.1.2.7 2000/06/26 02:04:05 sommerfeld Exp $ */
 
 /*-
@@ -406,8 +406,7 @@ cpu_init(struct cpu_info *ci)
        patinit(ci);
  
        /*
-        * Enable ring 0 write protection (486 or above, but 386
-        * no longer supported).
+        * Enable ring 0 write protection.
         */
        lcr0(rcr0() | CR0_WP);
 

diff --git a/sys/arch/i386/i386/lapic.c b/sys/arch/i386/i386/lapic.c
index e995106..c7de8ea 100644 (file)
--- a/sys/arch/i386/i386/lapic.c
+++ b/sys/arch/i386/i386/lapic.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: lapic.c,v 1.48 2021/06/11 05:33:16 jsg Exp $  */
+/*     $OpenBSD: lapic.c,v 1.49 2022/08/15 04:17:50 daniel Exp $       */
 /* $NetBSD: lapic.c,v 1.1.2.8 2000/02/23 06:10:50 sommerfeld Exp $ */
 
 /*-
@@ -85,8 +85,7 @@ lapic_map(paddr_t lapic_base)
        tpr = lapic_tpr;
 
        /*
-        * Map local apic.  If we have a local apic, it's safe to assume
-        * we're on a 486 or better and can use invlpg and non-cacheable PTEs
+        * Map local apic.
         *
         * Whap the PTE "by hand" rather than calling pmap_kenter_pa because
         * the latter will attempt to invoke TLB shootdown code just as we

diff --git a/sys/arch/i386/i386/locore.s b/sys/arch/i386/i386/locore.s
index cf52a79..e0753e7 100644 (file)
--- a/sys/arch/i386/i386/locore.s
+++ b/sys/arch/i386/i386/locore.s
@@ -1,4 +1,4 @@
-/*     $OpenBSD: locore.s,v 1.194 2022/01/03 00:44:30 jsg Exp $        */
+/*     $OpenBSD: locore.s,v 1.195 2022/08/15 04:17:50 daniel Exp $     */
 /*     $NetBSD: locore.s,v 1.145 1996/05/03 19:41:19 christos Exp $    */
 
 /*-
@@ -266,7 +266,7 @@ _C_LABEL(lapic_tpr):
        .long   0
 #endif
 
-_C_LABEL(cpu):         .long   0       # are we 386, 386sx, 486, 586 or 686
+_C_LABEL(cpu):         .long   0       # are we 486, 586 or 686
 _C_LABEL(cpu_id):      .long   0       # saved from 'cpuid' instruction
 _C_LABEL(cpu_pae):     .long   0       # are we using PAE paging mode?
 _C_LABEL(cpu_miscinfo):        .long   0       # misc info (apic/brand id) from 'cpuid'

diff --git a/sys/arch/i386/i386/locore0.S b/sys/arch/i386/i386/locore0.S
index 2cd0dd9..2e68fc0 100644 (file)
--- a/sys/arch/i386/i386/locore0.S
+++ b/sys/arch/i386/i386/locore0.S
@@ -1,4 +1,4 @@
-/*     $OpenBSD: locore0.S,v 1.6 2022/07/07 00:56:46 daniel Exp $      */
+/*     $OpenBSD: locore0.S,v 1.7 2022/08/15 04:17:50 daniel Exp $      */
 /*     $NetBSD: locore.s,v 1.145 1996/05/03 19:41:19 christos Exp $    */
 
 /*-
@@ -115,27 +115,6 @@ start:     movw    $0x1234,0x472                   # warm boot
 
        /* Find out our CPU type. */
 
-.Ltry386:      /* Try to toggle alignment check flag; does not exist on 386. */
-       pushfl
-       popl    %eax
-       movl    %eax,%ecx
-       orl     $PSL_AC,%eax
-       pushl   %eax
-       popfl
-       pushfl
-       popl    %eax
-       xorl    %ecx,%eax
-       andl    $PSL_AC,%eax
-       pushl   %ecx
-       popfl
-
-       testl   %eax,%eax
-       jnz     .Ltry486
-
-.Lis386:
-       movl    $CPU_386,RELOC(_C_LABEL(cpu))
-       jmp     2f
-
 .Ltry486:      /* Try to toggle identification flag; does not exist on early 486s. */
        pushfl
        popl    %eax

diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index 9b0f5db..e4cb15b 100644 (file)
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: machdep.c,v 1.651 2022/07/27 01:44:25 daniel Exp $    */
+/*     $OpenBSD: machdep.c,v 1.652 2022/08/15 04:17:50 daniel Exp $    */
 /*     $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $    */
 
 /*-
@@ -498,10 +498,6 @@ char       cpu_model[120];
  * We deal with the rest in a different way.
  */
 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
-       { CPUVENDOR_INTEL, "Intel", "386SX",    CPUCLASS_386,
-               NULL},                          /* CPU_386SX */
-       { CPUVENDOR_INTEL, "Intel", "386DX",    CPUCLASS_386,
-               NULL},                          /* CPU_386   */
        { CPUVENDOR_INTEL, "Intel", "486SX",    CPUCLASS_486,
                NULL},                          /* CPU_486SX */
        { CPUVENDOR_INTEL, "Intel", "486DX",    CPUCLASS_486,
@@ -513,7 +509,6 @@ const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
 };
 
 const char *classnames[] = {
-       "386",
        "486",
        "586",
        "686"
@@ -1673,7 +1668,7 @@ void
 identifycpu(struct cpu_info *ci)
 {
        const char *name, *modifier, *vendorname, *token;
-       int class = CPUCLASS_386, vendor, i, max;
+       int class = CPUCLASS_486, vendor, i, max;
        int family, model, step, modif, cachesize;
        const struct cpu_cpuid_nameclass *cpup = NULL;
        char *brandstr_from, *brandstr_to;
@@ -2078,19 +2073,13 @@ identifycpu(struct cpu_info *ci)
 
        cpu_class = class;
 
-       if (cpu_class == CPUCLASS_386) {
-               printf("WARNING: 386 (possibly unknown?) cpu class, assuming 486\n");
-               cpu_class = CPUCLASS_486;
-       }
-
        ci->cpu_class = class;
 
        if (cpu == CPU_486DLC)
                printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
 
        /*
-        * Enable ring 0 write protection (486 or above, but 386
-        * no longer supported).
+        * Enable ring 0 write protection.
         */
        lcr0(rcr0() | CR0_WP);
 

diff --git a/sys/arch/i386/include/cputypes.h b/sys/arch/i386/include/cputypes.h
index df6b2d7..26f50e8 100644 (file)
--- a/sys/arch/i386/include/cputypes.h
+++ b/sys/arch/i386/include/cputypes.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: cputypes.h,v 1.12 2022/07/27 01:44:25 daniel Exp $    */
+/*     $OpenBSD: cputypes.h,v 1.13 2022/08/15 04:17:51 daniel Exp $    */
 /*     $NetBSD: cputypes.h,v 1.10 1997/10/18 04:51:03 mikel Exp $      */
 
 /*
@@ -32,7 +32,6 @@
  *     Classes of Processor
  */
 
-#define        CPUCLASS_386    0
 #define        CPUCLASS_486    1
 #define        CPUCLASS_586    2
 #define        CPUCLASS_686    3
@@ -42,8 +41,6 @@
  * that might not have a cpuid instruction.
  */
 
-#define        CPU_386SX       0       /* Intel 80386SX */
-#define        CPU_386         1       /* Intel 80386DX */
 #define        CPU_486SX       2       /* Intel 80486SX */
 #define        CPU_486         3       /* Intel 80486DX */
 #define        CPU_486DLC      4       /* Cyrix 486DLC */

diff --git a/sys/arch/i386/stand/mbr/mbr.S b/sys/arch/i386/stand/mbr/mbr.S
index e234d9d..82c08f5 100644 (file)
--- a/sys/arch/i386/stand/mbr/mbr.S
+++ b/sys/arch/i386/stand/mbr/mbr.S
@@ -1,4 +1,4 @@
-/*     $OpenBSD: mbr.S,v 1.25 2022/06/27 16:10:09 deraadt Exp $        */
+/*     $OpenBSD: mbr.S,v 1.26 2022/08/15 04:17:51 daniel Exp $ */
 
 /*
  * Copyright (c) 1997 Michael Shalayeff and Tobias Weingartner
@@ -112,7 +112,7 @@ start:
         *
         * Accordingly, this code will fail on very early 8086/88s, but
         * nick@ will just have to live with it.  Others will note that
-        * we require an 80386 (or compatible) or above processor, anyway.
+        * we require at least a Pentium compatible processor anyway.
         */
        /* cli */
        movw    %ax, %ss