Add some more RK3588 PCIe clocks and resets.

ok kettenis@

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index d11c104..1655fbb 100644 (file)
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: rkclock.c,v 1.81 2023/07/08 08:37:39 patrick Exp $    */
+/*     $OpenBSD: rkclock.c,v 1.82 2023/07/09 16:33:49 patrick Exp $    */
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -4172,17 +4172,47 @@ const struct rkclock rk3588_clocks[] = {
                RK3588_CLK_REF_PIPE_PHY0_OSC_SRC, 0, 0, 0,
                { RK3588_XIN24M }
        },
+       {
+               RK3588_CLK_REF_PIPE_PHY1_OSC_SRC, 0, 0, 0,
+               { RK3588_XIN24M }
+       },
+       {
+               RK3588_CLK_REF_PIPE_PHY2_OSC_SRC, 0, 0, 0,
+               { RK3588_XIN24M }
+       },
        {
                RK3588_CLK_REF_PIPE_PHY0_PLL_SRC, RK3588_CRU_CLKSEL_CON(176),
                0, DIV(5, 0),
                { RK3588_PLL_PPLL }
        },
+       {
+               RK3588_CLK_REF_PIPE_PHY1_PLL_SRC, RK3588_CRU_CLKSEL_CON(176),
+               0, DIV(11, 6),
+               { RK3588_PLL_PPLL }
+       },
+       {
+               RK3588_CLK_REF_PIPE_PHY2_PLL_SRC, RK3588_CRU_CLKSEL_CON(177),
+               0, DIV(5, 0),
+               { RK3588_PLL_PPLL }
+       },
        {
                RK3588_CLK_REF_PIPE_PHY0, RK3588_CRU_CLKSEL_CON(177),
                SEL(6, 6), 0,
                { RK3588_CLK_REF_PIPE_PHY0_OSC_SRC,
                  RK3588_CLK_REF_PIPE_PHY0_PLL_SRC },
        },
+       {
+               RK3588_CLK_REF_PIPE_PHY1, RK3588_CRU_CLKSEL_CON(177),
+               SEL(7, 7), 0,
+               { RK3588_CLK_REF_PIPE_PHY1_OSC_SRC,
+                 RK3588_CLK_REF_PIPE_PHY1_PLL_SRC },
+       },
+       {
+               RK3588_CLK_REF_PIPE_PHY2, RK3588_CRU_CLKSEL_CON(177),
+               SEL(8, 8), 0,
+               { RK3588_CLK_REF_PIPE_PHY2_OSC_SRC,
+                 RK3588_CLK_REF_PIPE_PHY2_PLL_SRC },
+       },
        {
                /* Sentinel */
        }
@@ -4440,10 +4470,26 @@ rk3588_reset(void *cookie, uint32_t *cells, int on)
                reg = RK3588_CRU_SOFTRST_CON(77);
                bit = 6;
                break;
+       case RK3588_SRST_REF_PIPE_PHY1:
+               reg = RK3588_CRU_SOFTRST_CON(77);
+               bit = 7;
+               break;
+       case RK3588_SRST_REF_PIPE_PHY2:
+               reg = RK3588_CRU_SOFTRST_CON(77);
+               bit = 8;
+               break;
        case RK3588_SRST_P_PCIE2_PHY0:
                reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
                bit = 5;
                break;
+       case RK3588_SRST_P_PCIE2_PHY1:
+               reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
+               bit = 6;
+               break;
+       case RK3588_SRST_P_PCIE2_PHY2:
+               reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
+               bit = 7;
+               break;
        case RK3588_SRST_PCIE30_PHY:
                reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
                bit = 10;

diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 6ca83f5..55f696f 100644 (file)
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -471,8 +471,14 @@
 #define RK3588_CLK_UART0               666
 #define RK3588_SCLK_UART0              667
 #define RK3588_CLK_REF_PIPE_PHY0_OSC_SRC 674
+#define RK3588_CLK_REF_PIPE_PHY1_OSC_SRC 675
+#define RK3588_CLK_REF_PIPE_PHY2_OSC_SRC 676
 #define RK3588_CLK_REF_PIPE_PHY0_PLL_SRC 677
+#define RK3588_CLK_REF_PIPE_PHY1_PLL_SRC 678
+#define RK3588_CLK_REF_PIPE_PHY2_PLL_SRC 679
 #define RK3588_CLK_REF_PIPE_PHY0       680
+#define RK3588_CLK_REF_PIPE_PHY1       681
+#define RK3588_CLK_REF_PIPE_PHY2       682
 
 #define RK3588_PLL_SPLL                        1022
 #define RK3588_XIN24M                  1023
@@ -490,5 +496,9 @@
 #define RK3588_SRST_A_USB3OTG0         338
 #define RK3588_SRST_A_USB3OTG1         339
 #define RK3588_SRST_REF_PIPE_PHY0      572
+#define RK3588_SRST_REF_PIPE_PHY1      573
+#define RK3588_SRST_REF_PIPE_PHY2      574
 #define RK3588_SRST_P_PCIE2_PHY0       579
+#define RK3588_SRST_P_PCIE2_PHY1       580
+#define RK3588_SRST_P_PCIE2_PHY2       581
 #define RK3588_SRST_PCIE30_PHY         584