#define MDP_STACKADJ 0x0002 /* Frame SP adjusted, might have to
undo when system call returns
ERESTART. */
+#define MDP_UNCACHE_WX 0x0004 /* The process might modify code, so
+ don't cache writeable executable pages. */
#include <dev/cons.h>
+#ifdef COMPAT_SUNOS
+#include <compat/sunos/sunos_syscall.h>
+extern struct emul emul_sunos;
+#endif
+
#include "via.h"
#include "macrom.h"
#include "ether.h"
if (fpu_type) {
m68881_restore(&p->p_addr->u_pcb.pcb_fpregs);
}
+
+#ifdef COMPAT_SUNOS
+ /*
+ * SunOS' ld.so does self-modifying code without knowing
+ * about the 040's cache purging needs. So we need to uncache
+ * writeable executable pages.
+ */
+ if (p->p_emul == &emul_sunos)
+ p->p_md.md_flags |= MDP_UNCACHE_WX;
+ else
+ p->p_md.md_flags &= ~MDP_UNCACHE_WX;
+#endif
}
#define SS_RTEFRAME 1
npte = pa | pte_prot(pmap, prot) | (*pte & (PG_M|PG_U)) | PG_V;
if (wired)
npte |= PG_W;
+
+ /* Don't cache if process can't take it, like SunOS ones. */
+ if (mmutype == MMU_68040 && pmap != pmap_kernel() &&
+ (curproc->p_md.md_flags & MDP_UNCACHE_WX) &&
+ (prot & VM_PROT_EXECUTE) && (prot & VM_PROT_WRITE))
+ checkpv = cacheable = FALSE;
+
if (!checkpv && !cacheable)
npte |= PG_CI;
#if defined(M68040)