Add SPI clocks for other 64-bit Rockchip SoCs.

ok jsg@, deraadt@

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index 653c164..e7ee863 100644 (file)
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: rkclock.c,v 1.86 2024/03/02 19:48:13 kettenis Exp $   */
+/*     $OpenBSD: rkclock.c,v 1.87 2024/03/06 14:55:22 kettenis Exp $   */
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -1043,6 +1043,21 @@ const struct rkclock rk3308_clocks[] = {
                SEL(15, 14), DIV(6, 0),
                { RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
        },
+       {
+               RK3308_CLK_SPI0, RK3308_CRU_CLKSEL_CON(30),
+               SEL(15, 14), DIV(6, 0),
+               { RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
+       },
+       {
+               RK3308_CLK_SPI1, RK3308_CRU_CLKSEL_CON(31),
+               SEL(15, 14), DIV(6, 0),
+               { RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
+       },
+       {
+               RK3308_CLK_SPI2, RK3308_CRU_CLKSEL_CON(32),
+               SEL(15, 14), DIV(6, 0),
+               { RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
+       },
        {
                RK3308_CLK_TSADC, RK3308_CRU_CLKSEL_CON(33),
                0, DIV(10, 0),
@@ -1531,6 +1546,11 @@ const struct rkclock rk3328_clocks[] = {
                SEL(15, 14), DIV(13, 0),
                { RK3328_PLL_CPLL, RK3328_PLL_GPLL, RK3328_XIN24M }
        },
+       {
+               RK3328_CLK_SPI, RK3328_CRU_CLKSEL_CON(24),
+               SEL(7, 7), DIV(6, 0),
+               { RK3328_PLL_CPLL, RK3328_PLL_GPLL }
+       },
        {
                RK3328_CLK_SDMMC, RK3328_CRU_CLKSEL_CON(30),
                SEL(9, 8), DIV(7, 0),
@@ -2256,6 +2276,31 @@ const struct rkclock rk3399_clocks[] = {
                SEL(15, 15), DIV(14, 8),
                { RK3399_PLL_CPLL, RK3399_PLL_GPLL }
        },
+       {
+               RK3399_CLK_SPI0, RK3399_CRU_CLKSEL_CON(59),
+               SEL(7, 7), DIV(6, 0),
+               { RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+       },
+       {
+               RK3399_CLK_SPI1, RK3399_CRU_CLKSEL_CON(59),
+               SEL(15, 15), DIV(14, 8),
+               { RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+       },
+       {
+               RK3399_CLK_SPI2, RK3399_CRU_CLKSEL_CON(60),
+               SEL(7, 7), DIV(6, 0),
+               { RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+       },
+       {
+               RK3399_CLK_SPI4, RK3399_CRU_CLKSEL_CON(60),
+               SEL(15, 15), DIV(14, 8),
+               { RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+       },
+       {
+               RK3399_CLK_SPI5, RK3399_CRU_CLKSEL_CON(58),
+               SEL(15, 15), DIV(14, 8),
+               { RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+       },
        {
                RK3399_CLK_SDMMC, RK3399_CRU_CLKSEL_CON(16),
                SEL(10, 8), DIV(6, 0),
@@ -3284,6 +3329,26 @@ const struct rkclock rk3568_clocks[] = {
                RK3568_CLK_I2C5, 0, 0, 0,
                { RK3568_CLK_I2C }
        },
+       {
+               RK3568_CLK_SPI0, RK3568_CRU_CLKSEL_CON(72),
+               SEL(1, 0), 0,
+               { RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
+       },
+       {
+               RK3568_CLK_SPI1, RK3568_CRU_CLKSEL_CON(72),
+               SEL(3, 2), 0,
+               { RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
+       },
+       {
+               RK3568_CLK_SPI2, RK3568_CRU_CLKSEL_CON(72),
+               SEL(5, 4), 0,
+               { RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
+       },
+       {
+               RK3568_CLK_SPI3, RK3568_CRU_CLKSEL_CON(72),
+               SEL(7, 6), 0,
+               { RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
+       },
        {
                RK3568_SCLK_GMAC0, RK3568_CRU_CLKSEL_CON(31),
                SEL(2, 2), 0,

diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 423fbbe..7a593c4 100644 (file)
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -57,6 +57,9 @@
 #define RK3308_CLK_UART3               20
 #define RK3308_CLK_UART4               21
 #define RK3308_CLK_PWM0                        26
+#define RK3308_CLK_SPI0                        27
+#define RK3308_CLK_SPI1                        28
+#define RK3308_CLK_SPI2                        29
 #define RK3308_CLK_TSADC               36
 #define RK3308_CLK_SARADC              37
 #define RK3308_CLK_CRYPTO              41
@@ -103,6 +106,7 @@
 #define RK3328_ARMCLK                  6
 
 #define RK3328_CLK_RTC32K              30
+#define RK3328_CLK_SPI                 32
 #define RK3328_CLK_SDMMC               33
 #define RK3328_CLK_SDIO                        34
 #define RK3328_CLK_EMMC                        35
@@ -171,6 +175,11 @@
 #define RK3399_CLK_I2C5                        68
 #define RK3399_CLK_I2C6                        69
 #define RK3399_CLK_I2C7                        70
+#define RK3399_CLK_SPI0                        71
+#define RK3399_CLK_SPI1                        72
+#define RK3399_CLK_SPI2                        73
+#define RK3399_CLK_SPI4                        74
+#define RK3399_CLK_SPI5                        75
 #define RK3399_CLK_SDMMC               76
 #define RK3399_CLK_SDIO                        77
 #define RK3399_CLK_EMMC                        78
@@ -326,6 +335,10 @@
 #define RK3568_CLK_I2C3                        332
 #define RK3568_CLK_I2C4                        334
 #define RK3568_CLK_I2C5                        336
+#define RK3568_CLK_SPI0                        338
+#define RK3568_CLK_SPI1                        340
+#define RK3568_CLK_SPI2                        342
+#define RK3568_CLK_SPI3                        344
 #define RK3568_SCLK_GMAC0              386
 #define RK3568_SCLK_GMAC0_RGMII_SPEED  387
 #define RK3568_SCLK_GMAC0_RMII_SPEED   388