drm/amd/display: Update number of DCN3 clock states

From Aurabindo Pillai
583c4f3d09c3e980a683b59febbb0c775bdff1db in linux 5.10.y/5.10.67
0bbf06d888734041e813b916d7821acd4f72005a in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
index e5f4f93..fcb2e1f 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2522,6 +2522,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
                        dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
                }
 
+               dcn3_0_soc.num_states = num_states;
                for (i = 0; i < dcn3_0_soc.num_states; i++) {
                        dcn3_0_soc.clock_limits[i].state = i;
                        dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];