The ARMv7 architecture deprecates the separate Instruction and Data TLB

maintanenance instruction and recommends to only use the instructions that
operate on the unified TLB.  Those instructions will flush both TLBs on
implementations that still have separate Instruction and Data TLBs.  Switch
the TLB maintenance primitives over to use those.  This allows us to reduce
the number of primitives on armv7.  We still keep separate "ID" and "D"
variants as we still have to flush the branch predictor when changing the
mappings of pages that contain instructions.

ok jsg@

diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
index 18c323e..92dec59 100644 (file)
--- a/sys/arch/arm/arm/cpufunc.c
+++ b/sys/arch/arm/arm/cpufunc.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: cpufunc.c,v 1.42 2016/07/31 03:49:51 jsg Exp $        */
+/*     $OpenBSD: cpufunc.c,v 1.43 2016/08/03 07:05:05 kettenis Exp $   */
 /*     $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */
 
 /*
@@ -109,8 +109,8 @@ struct cpu_functions armv7_cpufuncs = {
 
        armv7_tlb_flushID,              /* tlb_flushID          */
        armv7_tlb_flushID_SE,           /* tlb_flushID_SE       */
-       armv7_tlb_flushI,               /* tlb_flushI           */
-       armv7_tlb_flushI_SE,            /* tlb_flushI_SE        */
+       armv7_tlb_flushID,              /* tlb_flushI           */
+       armv7_tlb_flushID_SE,           /* tlb_flushI_SE        */
        armv7_tlb_flushD,               /* tlb_flushD           */
        armv7_tlb_flushD_SE,            /* tlb_flushD_SE        */
 

diff --git a/sys/arch/arm/arm/cpufunc_asm_armv7.S b/sys/arch/arm/arm/cpufunc_asm_armv7.S
index 6a6eeb1..f1d4383 100644 (file)
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpufunc_asm_armv7.S,v 1.10 2016/04/25 04:46:56 jsg Exp $ */
+/* $OpenBSD: cpufunc_asm_armv7.S,v 1.11 2016/08/03 07:05:05 kettenis Exp $ */
 /*
  * Copyright (c) 2008 Dale Rahn <drahn@openbsd.org>
  *
@@ -45,7 +45,7 @@ ENTRY(armv7_setttb)
        isb     sy
 
        mcr     CP15_TTBR0(r0)          /* load new TTB */
-       mcr     CP15_TLBIALL(r0)        /* invalidate I+D TLBs */
+       mcr     CP15_TLBIALL(r0)        /* invalidate unified TLB */
        dsb     sy
        isb     sy
 
@@ -55,45 +55,27 @@ ENTRY(armv7_setttb)
  * TLB functions
  */
 ENTRY(armv7_tlb_flushID_SE)
-       mcr     CP15_DTLBIMVA           /* flush D tlb single entry */
-       mcr     CP15_ITLBIMVA           /* flush I tlb single entry */
+       mcr     CP15_TLBIMVA(r0)        /* flush unified tlb single entry */
        mcr     CP15_BPIMVA             /* flush va from BP */
        dsb     sy
        isb     sy
        mov     pc, lr
 
-ENTRY(armv7_tlb_flushI_SE)
-       mcr     CP15_ITLBIMVA           /* flush I tlb single entry */
-       mcr     CP15_BPIMVA             /* flush va from BP */
-       dsb     sy
-       isb     sy
-       mov     pc, lr
-
-/*
- * TLB functions
- */
 ENTRY(armv7_tlb_flushID)
-       mcr     CP15_TLBIALL(r0)        /* flush I+D tlb */
+       mcr     CP15_TLBIALL(r0)        /* flush unified tlb */
        mcr     CP15_BPIALL             /* Flush BP cache */
        dsb     sy
        isb     sy
        mov     pc, lr
 
-ENTRY(armv7_tlb_flushI)
-       mcr     CP15_ITLBIALL           /* flush I tlb */
-       mcr     CP15_BPIALL             /* Flush BP cache */
+ENTRY(armv7_tlb_flushD_SE)
+       mcr     CP15_TLBIMVA(r0)        /* flush unified tlb single entry */
        dsb     sy
        isb     sy
        mov     pc, lr
 
 ENTRY(armv7_tlb_flushD)
-       mcr     CP15_DTLBIALL           /* flush D tlb */
-       dsb     sy
-       isb     sy
-       mov     pc, lr
-
-ENTRY(armv7_tlb_flushD_SE)
-       mcr     CP15_DTLBIMVA           /* flush D tlb single entry */
+       mcr     CP15_TLBIALL(r0)        /* flush unified tlb */
        dsb     sy
        isb     sy
        mov     pc, lr
@@ -251,7 +233,7 @@ ENTRY(armv7_context_switch)
        isb     sy
 
        mcr     CP15_TTBR0(r0)          /* set the new TTB */
-       mcr     CP15_TLBIALL(r0)        /* and flush the I+D tlbs */
+       mcr     CP15_TLBIALL(r0)        /* and flush the unified tlb */
        dsb     sy
        isb     sy
        mov     pc, lr