Add a few more RK3588 clocks/resets that are reference by newer device

trees.

ok dlg@

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index 17a62a6..b28808a 100644 (file)
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: rkclock.c,v 1.83 2023/09/29 15:51:48 kettenis Exp $   */
+/*     $OpenBSD: rkclock.c,v 1.84 2023/11/26 13:47:45 kettenis Exp $   */
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -4107,6 +4107,11 @@ const struct rkclock rk3588_clocks[] = {
                { RK3588_CLK_GPU_SRC },
                SET_PARENT
        },
+       {
+               RK3588_CCLK_SRC_SDIO, RK3588_CRU_CLKSEL_CON(172),
+               SEL(9, 8), DIV(7, 2),
+               { RK3588_PLL_GPLL, RK3588_PLL_CPLL, RK3588_XIN24M }
+       },
        {
                RK3588_ACLK_VOP_ROOT, RK3588_CRU_CLKSEL_CON(110),
                SEL(7, 5), DIV(4, 0),
@@ -4292,6 +4297,9 @@ rk3588_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)
        case 1188000000U:
                p = 2; m = 198; s = 1; k = 0;
                break;
+       case 1100000000U:
+               p = 3; m = 550; s = 2; k = 0;
+               break;
        case 850000000U:
                p = 3; m = 425; s = 2; k = 0;
                break;
@@ -4476,6 +4484,10 @@ rk3588_reset(void *cookie, uint32_t *cells, int on)
                reg = RK3588_CRU_SOFTRST_CON(34);
                bit = 0;
                break;
+       case RK3588_SRST_A_USB3OTG2:
+               reg = RK3588_CRU_SOFTRST_CON(35);
+               bit = 7;
+               break;
        case RK3588_SRST_A_USB3OTG0:
                reg = RK3588_CRU_SOFTRST_CON(42);
                bit = 4;

diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index d55078e..67f61e7 100644 (file)
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -458,6 +458,7 @@
 #define RK3588_ACLK_LOW_TOP_ROOT       258
 #define RK3588_CLK_GPU_SRC             261
 #define RK3588_CLK_GPU                 262
+#define RK3588_CCLK_SRC_SDIO           395
 #define RK3588_ACLK_VOP_ROOT           600
 #define RK3588_ACLK_VOP                        605
 #define RK3588_ACLK_VOP_SUB_SRC                619
@@ -497,6 +498,7 @@
 #define RK3588_SRST_P_PCIE2            301
 #define RK3588_SRST_P_PCIE3            302
 #define RK3588_SRST_P_PCIE4            303
+#define RK3588_SRST_A_USB3OTG2         308
 #define RK3588_SRST_A_USB3OTG0         338
 #define RK3588_SRST_A_USB3OTG1         339
 #define RK3588_SRST_REF_PIPE_PHY0      572