drm/i915/rpl-p: Add PCI IDs
authorjsg <jsg@openbsd.org>
Thu, 26 May 2022 01:41:16 +0000 (01:41 +0000)
committerjsg <jsg@openbsd.org>
Thu, 26 May 2022 01:41:16 +0000 (01:41 +0000)
From Matt Atwood
72c3c8d6e5275b19fd2d32ec787e8135a421c7ec in mainline linux

sys/dev/pci/drm/i915/i915_drv.h
sys/dev/pci/drm/i915/i915_pci.c
sys/dev/pci/drm/i915/intel_device_info.c
sys/dev/pci/drm/i915/intel_device_info.h
sys/dev/pci/drm/include/drm/i915_pciids.h

index 33f46d8..8f89fa9 100644 (file)
@@ -1527,9 +1527,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2_G11(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_ADLS_RPLS(dev_priv) \
-       IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
+       IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
+#define IS_ADLP_RPLP(dev_priv) \
+       IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
                                    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
index 708d702..bea2fe6 100644 (file)
@@ -1117,6 +1117,7 @@ const struct pci_device_id pciidlist[] = {
        INTEL_ADLP_IDS(&adl_p_info),
        INTEL_ADLN_IDS(&adl_p_info),
        INTEL_RPLS_IDS(&adl_s_info),
+       INTEL_RPLP_IDS(&adl_p_info),
        {0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
index cb55cdb..1a5989f 100644 (file)
@@ -181,8 +181,9 @@ static const u16 subplatform_n_ids[] = {
        INTEL_ADLN_IDS(0),
 };
 
-static const u16 subplatform_rpls_ids[] = {
+static const u16 subplatform_rpl_ids[] = {
        INTEL_RPLS_IDS(0),
+       INTEL_RPLP_IDS(0),
 };
 
 static bool find_devid(u16 id, const u16 *p, unsigned int num)
@@ -224,9 +225,9 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
        } else if (find_devid(devid, subplatform_n_ids,
                                ARRAY_SIZE(subplatform_n_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_N);
-       } else if (find_devid(devid, subplatform_rpls_ids,
-                             ARRAY_SIZE(subplatform_rpls_ids))) {
-               mask = BIT(INTEL_SUBPLATFORM_RPL_S);
+       } else if (find_devid(devid, subplatform_rpl_ids,
+                             ARRAY_SIZE(subplatform_rpl_ids))) {
+               mask = BIT(INTEL_SUBPLATFORM_RPL);
        }
 
        if (IS_TIGERLAKE(i915)) {
index 359825e..c9bd413 100644 (file)
@@ -110,11 +110,16 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_G10  0
 #define INTEL_SUBPLATFORM_G11  1
 
-/* ADL-S */
-#define INTEL_SUBPLATFORM_RPL_S        0
+/* ADL */
+#define INTEL_SUBPLATFORM_RPL  0
 
 /* ADL-P */
-#define INTEL_SUBPLATFORM_N    0
+/*
+ * As #define INTEL_SUBPLATFORM_RPL 0 will apply
+ * here too, SUBPLATFORM_N will have different
+ * bit set
+ */
+#define INTEL_SUBPLATFORM_N    1
 
 enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
index 0800dc8..a7b5eea 100644 (file)
        INTEL_VGA_DEVICE(0xA78A, info), \
        INTEL_VGA_DEVICE(0xA78B, info)
 
+/* RPL-P */
+#define INTEL_RPLP_IDS(info) \
+       INTEL_VGA_DEVICE(0xA720, info), \
+       INTEL_VGA_DEVICE(0xA721, info), \
+       INTEL_VGA_DEVICE(0xA7A0, info), \
+       INTEL_VGA_DEVICE(0xA7A1, info), \
+       INTEL_VGA_DEVICE(0xA7A8, info), \
+       INTEL_VGA_DEVICE(0xA7A9, info)
+
 #endif /* _I915_PCIIDS_H */