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add missing break
author
jsg
<jsg@openbsd.org>
Fri, 23 Apr 2021 04:35:54 +0000
(
04:35
+0000)
committer
jsg
<jsg@openbsd.org>
Fri, 23 Apr 2021 04:35:54 +0000
(
04:35
+0000)
ok drahn@
sys/arch/riscv64/riscv64/fpu.c
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diff --git
a/sys/arch/riscv64/riscv64/fpu.c
b/sys/arch/riscv64/riscv64/fpu.c
index
076caaf
..
2128dc0
100644
(file)
--- a/
sys/arch/riscv64/riscv64/fpu.c
+++ b/
sys/arch/riscv64/riscv64/fpu.c
@@
-55,6
+55,7
@@
int fpu_valid_opcode(uint32_t instr)
case 0x2002: // C.FLDSP
// must verify dest register is float
valid = opcode16 & (1 << 11);
+ break;
case 0xa002: // C.FSDSP
// must verify dest register is float
valid = opcode16 & (1 << 6);