add missing break
authorjsg <jsg@openbsd.org>
Fri, 23 Apr 2021 04:35:54 +0000 (04:35 +0000)
committerjsg <jsg@openbsd.org>
Fri, 23 Apr 2021 04:35:54 +0000 (04:35 +0000)
ok drahn@

sys/arch/riscv64/riscv64/fpu.c

index 076caaf..2128dc0 100644 (file)
@@ -55,6 +55,7 @@ int fpu_valid_opcode(uint32_t instr)
                case 0x2002:    // C.FLDSP
                        // must verify dest register is float
                        valid = opcode16 & (1 << 11);
+                       break;
                case 0xa002:    // C.FSDSP
                        // must verify dest register is float
                        valid = opcode16 & (1 << 6);