-/* $OpenBSD: rtld_machine.c,v 1.43 2022/01/08 06:49:41 guenther Exp $ */
+/* $OpenBSD: rtld_machine.c,v 1.44 2022/08/29 02:08:13 jsg Exp $ */
/*
* Copyright (c) 2004 Michael Shalayeff
register long arg1 __asm__("r25") = sizeof(buf);
register long arg2 __asm__("r24") = 0xffffffff & (cookie >> 32);
register long arg3 __asm__("r23") = 0xffffffff & cookie;
- __asm__ __volatile__ ("ble 4(%%sr7, %%r1) ! ldi %0, %%r22"
+ __asm__ volatile ("ble 4(%%sr7, %%r1) ! ldi %0, %%r22"
:
: "i" (SYS_kbind), "r" (r1), "r"(arg0), "r"(arg1),
"r"(arg2), "r"(arg3)
-/* $OpenBSD: cache_mips64r2.c,v 1.3 2017/08/26 13:53:46 visa Exp $ */
+/* $OpenBSD: cache_mips64r2.c,v 1.4 2022/08/29 02:08:13 jsg Exp $ */
/*
* Copyright (c) 2014 Miodrag Vallat.
#define HitWBInvalidate_S 0x17
#define cache(op,addr) \
- __asm__ __volatile__ \
+ __asm__ volatile \
("cache %0, 0(%1)" :: "i"(op), "r"(addr) : "memory")
static __inline__ void mips64r2_hitinv_primary(vaddr_t, vsize_t, vsize_t);
}
#ifdef __amd64__
- __asm__ __volatile__ ("mov %0, %%r8" : : "r" (output_pa) : "r8");
- __asm__ __volatile__ ("call *%3" : "=a" (status) : "c" (control),
+ __asm__ volatile ("mov %0, %%r8" : : "r" (output_pa) : "r8");
+ __asm__ volatile ("call *%3" : "=a" (status) : "c" (control),
"d" (input_pa), "m" (sc->sc_hc));
#else /* __i386__ */
{
uint32_t status_hi = 1;
uint32_t status_lo = 1;
- __asm__ __volatile__ ("call *%8" :
+ __asm__ volatile ("call *%8" :
"=d" (status_hi), "=a"(status_lo) :
"d" (control_hi), "a" (control_lo),
"b" (0), "c" (input_pa), "D" (0), "S" (output_pa),