drm/amd/display: Fix surface optimization regression on Carrizo

From Nicholas Kazlauskas
c2b484d784c8dfc3eb62fd4f9ff11515b6e78e19 in linux 5.15.y/5.15.58
62e5a7e2333a9f5395f6a9db766b7b06c949fe7a in mainline linux

diff --git a/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c b/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c
index 46bef17..1bde9d4 100644 (file)
--- a/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c
+++ b/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c
@@ -2979,8 +2979,13 @@ void dc_commit_updates_for_stream(struct dc *dc,
                        if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
                                new_pipe->plane_state->force_full_update = true;
                }
-       } else if (update_type == UPDATE_TYPE_FAST) {
-               /* Previous frame finished and HW is ready for optimization. */
+       } else if (update_type == UPDATE_TYPE_FAST && dc_ctx->dce_version >= DCE_VERSION_MAX) {
+               /*
+                * Previous frame finished and HW is ready for optimization.
+                *
+                * Only relevant for DCN behavior where we can guarantee the optimization
+                * is safe to apply - retain the legacy behavior for DCE.
+                */
                dc_post_update_surfaces_to_stream(dc);
        }
 
@@ -3039,6 +3044,12 @@ void dc_commit_updates_for_stream(struct dc *dc,
                }
        }
 
+       /* Legacy optimization path for DCE. */
+       if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {
+               dc_post_update_surfaces_to_stream(dc);
+               TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
+       }
+
        return;
 
 }