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(parent: 8ab96db) | patch
The ARMv7 ARM says that the TLB may hold translation table entries at any
authorkettenis <kettenis@openbsd.org>
Thu, 11 Aug 2016 00:28:06 +0000 (00:28 +0000)
committerkettenis <kettenis@openbsd.org>
Thu, 11 Aug 2016 00:28:06 +0000 (00:28 +0000)
commitef4fdf74aa68d19a1ea493dbf5aa22ef6cb43bea
tree9aa65b1451fa150408bf18801d6ea1efb993f520tree | snapshot
parent8ab96db052fa2271faa75b1144933c873ecd92eccommit | diff
The ARMv7 ARM says that the TLB may hold translation table entries at any
level of the translation table, including entries that point to further
levels of the tables.  This means that we have to do a TLB flush whenever
we invalidate an L1 slot too.  Doing so fixes the pmap_fault_fixup
issue on Cortex-A7 processors.
sys/arch/arm/arm/pmap7.c diff | blob | history
OpenBSD src
by Ahmet Artu Yildirim