The INTSTS register is read-only, so the attempt to clear interrupts

The INTSTS register is read-only, so the attempt to clear interrupts
by writing to it doesn't actually work.  Therefore we have to keep
processing interrupts until all the bits corresponding to enabled
interrupts are cleared.  This makes MSIs actually work, also on the AMD
implementations for which we currently disable MSIs.

Based on some digging by martijn@

ok ratchov@, martijn@, stsp@