Instead of adjusting PLL0 to scale the CPU frequency, use the divider
authorkettenis <kettenis@openbsd.org>
Tue, 19 Sep 2023 19:15:08 +0000 (19:15 +0000)
committerkettenis <kettenis@openbsd.org>
Tue, 19 Sep 2023 19:15:08 +0000 (19:15 +0000)
commitd1efa468b4621baf72d8645ae750741c2ca6d85e
treeb83f9e4c21ab42bfa69fcab49ce502fc67b5599a
parentfdd80b3518f1be1c7e85d7fcb7df0fdc29f01c0a
Instead of adjusting PLL0 to scale the CPU frequency, use the divider
of the actual CPU clock.  This prevents one of the GMAC0 clocks changing
when we change the CPU frequency, which would break one of the Ethernet
ports on the VisionFive 2 v1.2a.

However, since the firmware configures PLL0 to 1 GHz, we still need to
bump it up to 1.5 GHz in order to reach the highest supported CPU clock
rates.

ok jmatthew@, jca@, jsing@
sys/arch/riscv64/dev/stfclock.c