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(parent: 3adb47d) | patch
Add support for the new layout of the CCSIDR_EL1 register that was
authorkettenis <kettenis@openbsd.org>
Mon, 18 Mar 2024 18:35:21 +0000 (18:35 +0000)
committerkettenis <kettenis@openbsd.org>
Mon, 18 Mar 2024 18:35:21 +0000 (18:35 +0000)
commitd1486c828a88fa44873debae38712f631570e6d1
treee9a31e555af497608437ffd54a09b7a697dea9d3tree | snapshot
parent3adb47df1f23cde39b699678ab6d0ef02ed4f9c5commit | diff
Add support for the new layout of the CCSIDR_EL1 register that was
introduced in Armv8.3 when the CCIDX feature is advertised.  This
makes us properly detect the cache size on newer CPU cores like
Neoverse N2, at least when emulated by QEMU.

ok jsg@
sys/arch/arm64/arm64/cpu.c diff | blob | history
sys/arch/arm64/include/armreg.h diff | blob | history
OpenBSD src
by Ahmet Artu Yildirim