Make ix(4) work on strict alignment architectures. The Intel networking

Make ix(4) work on strict alignment architectures.  The Intel networking
hardware is fairly retarded.  While it allows receive buffers with an
ETHER_ALIGN offset, it only allows the size of the buffers to be specified in
multiples of 1K.  This means that if we want to use standard mbuf clusters
we will waste 1024 - ETHER_ALIGN bytes per cluster, which is a lot for the
2K clusters we use now.  Compromise a bit by using 4K clusters on strict
alignment architectures and tell the hardware to use 3K of those, reducing
the spillage a bit.  While this isn't optimal, at least on sparc64 where we
have 8K pages, the pool page allocation overhead should be the same as on
amd64/i386 where we have 4K pages and continue to use 2K mbuf clusters.

ok mikeb@, dlg@