The "Avalanche" performance cores on Apple's M2 SoC have more than 16

The "Avalanche" performance cores on Apple's M2 SoC have more than 16
P-states.  As a result the layout of the "state" register changed.
Make the driver handle that.

Also make sure we use the correct lowest state in case the lowest
frequency of the performance cores is different from the lowest
frequency of the efficiency cores.

ok tobhe@