Add a instruction barrier between writing CCSELR_EL1 and reading CCSIDR_EL1

Add a instruction barrier between writing CCSELR_EL1 and reading CCSIDR_EL1
to guarantee that we read the cache parameters of the cache we just selected.
The required ISB instruction is present in the examples in the ARM ARM.
Fixes the the report on the cores in Apple's M1 SoC.

ok patrick@