The RISC-V architecture specification says that memory read/writes are

The RISC-V architecture specification says that memory read/writes are
not ordered with respect to mmio read/writes.  This appears to happen on
T-Head C920 cores as I'm seeing interrupts being enabled before the lock
is released in mtx_leave() despite program order releasing the lock
before enabling interrupts.  This is fixed by adding the necessary fences
in more or less the same places where Linux uses them.

ok patrick@, jca@