Implement uncached mappings on the StarFive JH7100 SoC, where the hardware
authorkettenis <kettenis@openbsd.org>
Mon, 17 Oct 2022 19:51:54 +0000 (19:51 +0000)
committerkettenis <kettenis@openbsd.org>
Mon, 17 Oct 2022 19:51:54 +0000 (19:51 +0000)
commit7d715679d8c63a626a7cb6dfb729f648afd65422
treee461f46c7206bce7e08653e206bfe28be3a300e9
parent62d244ed99f17c1263ee095bc7d8fa1f61df02fd
Implement uncached mappings on the StarFive JH7100 SoC, where the hardware
provides allows bypassing the L2 cache by using a physical address alias.

ok miod@
sys/arch/riscv64/riscv64/pmap.c