It turns out that there are seperate pins for the PCIe Gen 2 and 3, which
authorpatrick <patrick@openbsd.org>
Sun, 9 Jul 2023 19:11:30 +0000 (19:11 +0000)
committerpatrick <patrick@openbsd.org>
Sun, 9 Jul 2023 19:11:30 +0000 (19:11 +0000)
commit5b23ee9f7fff40c3a5d303a0cc3360a43360e931
tree74a38802c9917551d6dcc98c1e93f73937b5eefa
parentec216fe2d2cefdfbf22c1e7aa0935c00cddfd627
It turns out that there are seperate pins for the PCIe Gen 2 and 3, which
means that the x4 PCIe controller can get all PCIe Gen 3 lines, while the
others then only get PCIe Gen 2 lines.  Therefore the decision on how to
configure the mux needs to be adjusted so that the PCIe Gen 3 lines are
only routed to other PCIe controllers when they are explicitly configured
for them.  While there, fix an obvious typo.

ok kettenis@
sys/dev/fdt/rkpciephy.c