Wrong variable used in indexing meant that when a CPU's cache setup
authorguenther <guenther@openbsd.org>
Thu, 13 Jun 2024 02:19:20 +0000 (02:19 +0000)
committerguenther <guenther@openbsd.org>
Thu, 13 Jun 2024 02:19:20 +0000 (02:19 +0000)
commit4f0183c801faf589199b345284b042ba185379b1
tree3f0a1abe4ff25d2a0946fbac80bbb1d843dde42a
parentcd187d0bf5f90a5e9e8ee62ae93d04529dff09e2
Wrong variable used in indexing meant that when a CPU's cache setup
differed on the second or later cache, the generated dmesg didn't
report the earlier, identical cache levels correctly.

report, testing, and ok jsg@
sys/arch/amd64/amd64/cacheinfo.c