The clock on RISC-V is architectural, so we really don't need the

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers.  And we don't
really need a separate driver.  Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@