The StarFive JH7100 SoC found on the BeagleV beta boards has most of

The StarFive JH7100 SoC found on the BeagleV beta boards has most of
its peripherals hooked up through a bus that doesn't maintain cache
coherency.  So in order to use DMA we will need to flush the L2 caches
before/after a DMA tranfer.  Add a driver for the L2 cache controller
for these SoCs and infrastructure to do the necessary cache maintenance.
Since this particular L2 cache controller needs physical addresses, this
makes the bus_dma(4) code deviate from its arm64 counterpart.

ok drahn@