Add smmu(4), a driver the ARM System MMU. This IOMMU is basically a

Add smmu(4), a driver the ARM System MMU.  This IOMMU is basically a
regular ARM CPU MMU re-used for I/O devices.  Implementations can have a
mix of stage-2 only and stage-2/stage-2 context blocks (domains).  The
IOMMU allows different ways of grouping devices into a single domain.

This implementation only supports SMMUv2, since there is basically
no relevant SMMUv1 hardware.  It also only supports AArch64
pagetables, the same as our pmap.  Hence lots of code was taken from
there.  There is no support for 32-bit pagetables, which would have
also been needed for SMMUv1 support.  I have not yet seen any
machines with SMMUv3, which will probably need a new driver.

There is some work to be done, but the code works and it's about
time it hits the tree.

ok kettenis@