Now that we support RISC-V CPUs that have MMUs with memory cachability

Now that we support RISC-V CPUs that have MMUs with memory cachability
attributes, the "direct map" becomes problematic as it results in
mappings for the same physical memory pages with different cachability
addresses.  The RISC-V specification of the "Svpbmt" extension doesn't
outright state that this is "verboten" like on some other
architectures that we support.  But it does say that it may result in
access with the wrong attributes.  So restrict the use of the direct
map to just mapping the 64MB block that the bootloader loaded us into.
To make this possible map the device tree later like we do on arm64.
This allows us to get rid of some assembly code in locore.S as a bonus!

ok miod@, jca@