artulab.com Git - openbsd/blob

   1 from __future__ import print_function
   2 import lldb
   3 from lldbsuite.test.lldbtest import *
   4 from lldbsuite.test.decorators import *
   5 from gdbclientutils import *
   6
   7 class TestNestedRegDefinitions(GDBRemoteTestBase):
   8
   9     @skipIfXmlSupportMissing
  10     @skipIfRemote
  11     def test(self):
  12         """
  13         Test lldb's parsing of the <architecture> tag in the target.xml register
  14         description packet.
  15         """
  16         class MyResponder(MockGDBServerResponder):
  17
  18             def qXferRead(self, obj, annex, offset, length):
  19                 if annex == "target.xml":
  20                     return """<?xml version="1.0"?><!DOCTYPE target SYSTEM "gdb-target.dtd"><target><architecture>i386:x86-64</architecture><xi:include href="i386-64bit.xml"/></target>""", False
  21
  22                 if annex == "i386-64bit.xml":
  23                     return """<?xml version="1.0"?>
  24 <!-- Copyright (C) 2010-2017 Free Software Foundation, Inc.
  25
  26      Copying and distribution of this file, with or without modification,
  27      are permitted in any medium without royalty provided the copyright
  28      notice and this notice are preserved.  -->
  29
  30 <!-- I386 64bit -->
  31
  32 <!DOCTYPE target SYSTEM "gdb-target.dtd">
  33 <feature name="org.gnu.gdb.i386.64bit">
  34   <xi:include href="i386-64bit-core.xml"/>
  35   <xi:include href="i386-64bit-sse.xml"/>
  36 </feature>""", False
  37
  38                 if annex == "i386-64bit-core.xml":
  39                     return """<?xml version="1.0"?>
  40 <!-- Copyright (C) 2010-2015 Free Software Foundation, Inc.
  41
  42      Copying and distribution of this file, with or without modification,
  43      are permitted in any medium without royalty provided the copyright
  44      notice and this notice are preserved.  -->
  45
  46 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
  47 <feature name="org.gnu.gdb.i386.core">
  48   <flags id="i386_eflags" size="4">
  49     <field name="CF" start="0" end="0"/>
  50     <field name="" start="1" end="1"/>
  51     <field name="PF" start="2" end="2"/>
  52     <field name="AF" start="4" end="4"/>
  53     <field name="ZF" start="6" end="6"/>
  54     <field name="SF" start="7" end="7"/>
  55     <field name="TF" start="8" end="8"/>
  56     <field name="IF" start="9" end="9"/>
  57     <field name="DF" start="10" end="10"/>
  58     <field name="OF" start="11" end="11"/>
  59     <field name="NT" start="14" end="14"/>
  60     <field name="RF" start="16" end="16"/>
  61     <field name="VM" start="17" end="17"/>
  62     <field name="AC" start="18" end="18"/>
  63     <field name="VIF" start="19" end="19"/>
  64     <field name="VIP" start="20" end="20"/>
  65     <field name="ID" start="21" end="21"/>
  66   </flags>
  67
  68   <reg name="rax" bitsize="64" type="int64"/>
  69   <reg name="rbx" bitsize="64" type="int64"/>
  70   <reg name="rcx" bitsize="64" type="int64"/>
  71   <reg name="rdx" bitsize="64" type="int64"/>
  72   <reg name="rsi" bitsize="64" type="int64"/>
  73   <reg name="rdi" bitsize="64" type="int64"/>
  74   <reg name="rbp" bitsize="64" type="data_ptr"/>
  75   <reg name="rsp" bitsize="64" type="data_ptr"/>
  76   <reg name="r8" bitsize="64" type="int64"/>
  77   <reg name="r9" bitsize="64" type="int64"/>
  78   <reg name="r10" bitsize="64" type="int64"/>
  79   <reg name="r11" bitsize="64" type="int64"/>
  80   <reg name="r12" bitsize="64" type="int64"/>
  81   <reg name="r13" bitsize="64" type="int64"/>
  82   <reg name="r14" bitsize="64" type="int64"/>
  83   <reg name="r15" bitsize="64" type="int64"/>
  84
  85   <reg name="rip" bitsize="64" type="code_ptr"/>
  86   <reg name="eflags" bitsize="32" type="i386_eflags"/>
  87   <reg name="cs" bitsize="32" type="int32"/>
  88   <reg name="ss" bitsize="32" type="int32"/>
  89   <reg name="ds" bitsize="32" type="int32"/>
  90   <reg name="es" bitsize="32" type="int32"/>
  91   <reg name="fs" bitsize="32" type="int32"/>
  92   <reg name="gs" bitsize="32" type="int32"/>
  93
  94   <reg name="st0" bitsize="80" type="i387_ext"/>
  95   <reg name="st1" bitsize="80" type="i387_ext"/>
  96   <reg name="st2" bitsize="80" type="i387_ext"/>
  97   <reg name="st3" bitsize="80" type="i387_ext"/>
  98   <reg name="st4" bitsize="80" type="i387_ext"/>
  99   <reg name="st5" bitsize="80" type="i387_ext"/>
 100   <reg name="st6" bitsize="80" type="i387_ext"/>
 101   <reg name="st7" bitsize="80" type="i387_ext"/>
 102
 103   <reg name="fctrl" bitsize="32" type="int" group="float"/>
 104   <reg name="fstat" bitsize="32" type="int" group="float"/>
 105   <reg name="ftag" bitsize="32" type="int" group="float"/>
 106   <reg name="fiseg" bitsize="32" type="int" group="float"/>
 107   <reg name="fioff" bitsize="32" type="int" group="float"/>
 108   <reg name="foseg" bitsize="32" type="int" group="float"/>
 109   <reg name="fooff" bitsize="32" type="int" group="float"/>
 110   <reg name="fop" bitsize="32" type="int" group="float"/>
 111 </feature>""", False
 112
 113                 if annex == "i386-64bit-sse.xml":
 114                     return """<?xml version="1.0"?>
 115 <!-- Copyright (C) 2010-2017 Free Software Foundation, Inc.
 116
 117      Copying and distribution of this file, with or without modification,
 118      are permitted in any medium without royalty provided the copyright
 119      notice and this notice are preserved.  -->
 120
 121 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
 122 <feature name="org.gnu.gdb.i386.64bit.sse">
 123   <vector id="v4f" type="ieee_single" count="4"/>
 124   <vector id="v2d" type="ieee_double" count="2"/>
 125   <vector id="v16i8" type="int8" count="16"/>
 126   <vector id="v8i16" type="int16" count="8"/>
 127   <vector id="v4i32" type="int32" count="4"/>
 128   <vector id="v2i64" type="int64" count="2"/>
 129   <union id="vec128">
 130     <field name="v4_float" type="v4f"/>
 131     <field name="v2_double" type="v2d"/>
 132     <field name="v16_int8" type="v16i8"/>
 133     <field name="v8_int16" type="v8i16"/>
 134     <field name="v4_int32" type="v4i32"/>
 135     <field name="v2_int64" type="v2i64"/>
 136     <field name="uint128" type="uint128"/>
 137   </union>
 138   <flags id="i386_mxcsr" size="4">
 139     <field name="IE" start="0" end="0"/>
 140     <field name="DE" start="1" end="1"/>
 141     <field name="ZE" start="2" end="2"/>
 142     <field name="OE" start="3" end="3"/>
 143     <field name="UE" start="4" end="4"/>
 144     <field name="PE" start="5" end="5"/>
 145     <field name="DAZ" start="6" end="6"/>
 146     <field name="IM" start="7" end="7"/>
 147     <field name="DM" start="8" end="8"/>
 148     <field name="ZM" start="9" end="9"/>
 149     <field name="OM" start="10" end="10"/>
 150     <field name="UM" start="11" end="11"/>
 151     <field name="PM" start="12" end="12"/>
 152     <field name="FZ" start="15" end="15"/>
 153   </flags>
 154
 155   <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/>
 156   <reg name="xmm1" bitsize="128" type="vec128"/>
 157   <reg name="xmm2" bitsize="128" type="vec128"/>
 158   <reg name="xmm3" bitsize="128" type="vec128"/>
 159   <reg name="xmm4" bitsize="128" type="vec128"/>
 160   <reg name="xmm5" bitsize="128" type="vec128"/>
 161   <reg name="xmm6" bitsize="128" type="vec128"/>
 162   <reg name="xmm7" bitsize="128" type="vec128"/>
 163   <reg name="xmm8" bitsize="128" type="vec128"/>
 164   <reg name="xmm9" bitsize="128" type="vec128"/>
 165   <reg name="xmm10" bitsize="128" type="vec128"/>
 166   <reg name="xmm11" bitsize="128" type="vec128"/>
 167   <reg name="xmm12" bitsize="128" type="vec128"/>
 168   <reg name="xmm13" bitsize="128" type="vec128"/>
 169   <reg name="xmm14" bitsize="128" type="vec128"/>
 170   <reg name="xmm15" bitsize="128" type="vec128"/>
 171
 172   <reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
 173 </feature>""", False
 174
 175                 return None, False
 176
 177             def readRegister(self, regnum):
 178                 return ""
 179
 180             def readRegisters(self):
 181                 return "0600000000000000c0b7c00080fffffff021c60080ffffff1a00000000000000020000000000000078b7c00080ffffff203f8ca090ffffff103f8ca090ffffff3025990a80ffffff809698000000000070009f0a80ffffff020000000000000000eae10080ffffff00000000000000001822d74f1a00000078b7c00080ffffff0e12410080ffff004602000008000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f0300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000801f0000"
 182
 183             def haltReason(self):
 184                 return "T02thread:dead;threads:dead;"
 185
 186             def qfThreadInfo(self):
 187                 return "mdead"
 188
 189             def qC(self):
 190                 return ""
 191
 192             def qSupported(self, client_supported):
 193                 return "PacketSize=4000;qXfer:features:read+"
 194
 195             def QThreadSuffixSupported(self):
 196                 return "OK"
 197
 198             def QListThreadsInStopReply(self):
 199                 return "OK"
 200
 201         self.server.responder = MyResponder()
 202         if self.TraceOn():
 203             self.runCmd("log enable gdb-remote packets")
 204             self.addTearDownHook(
 205                     lambda: self.runCmd("log disable gdb-remote packets"))
 206
 207         target = self.dbg.CreateTargetWithFileAndArch(None, None)
 208
 209         process = self.connect(target)
 210
 211         if self.TraceOn():
 212             interp = self.dbg.GetCommandInterpreter()
 213             result = lldb.SBCommandReturnObject()
 214             interp.HandleCommand("target list", result)
 215             print(result.GetOutput())
 216
 217         rip_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("rip")
 218         self.assertEqual(rip_valobj.GetValueAsUnsigned(), 0x00ffff800041120e)
 219
 220         r15_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("r15")
 221         self.assertEqual(r15_valobj.GetValueAsUnsigned(), 0xffffff8000c0b778)
 222
 223         mxcsr_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("mxcsr")
 224         self.assertEqual(mxcsr_valobj.GetValueAsUnsigned(), 0x00001f80)
 225
 226         gpr_reg_set_name = process.GetThreadAtIndex(0).GetFrameAtIndex(0).GetRegisters().GetValueAtIndex(0).GetName()
 227         self.assertEqual(gpr_reg_set_name, "general")
 228
 229         float_reg_set_name = process.GetThreadAtIndex(0).GetFrameAtIndex(0).GetRegisters().GetValueAtIndex(1).GetName()
 230         self.assertEqual(float_reg_set_name, "float")
 231
 232         vector_reg_set_name = process.GetThreadAtIndex(0).GetFrameAtIndex(0).GetRegisters().GetValueAtIndex(2).GetName()
 233         self.assertEqual(vector_reg_set_name, "vector")
 234
 235         if self.TraceOn():
 236             print("rip is 0x%x" % rip_valobj.GetValueAsUnsigned())
 237             print("r15 is 0x%x" % r15_valobj.GetValueAsUnsigned())
 238             print("mxcsr is 0x%x" % mxcsr_valobj.GetValueAsUnsigned())